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rene s a s 4-bit c i sc s in g le- c hip mi c r oco mp u te r 4 500 s erie s 4502 group 4 rev. 2.01 revision date: feb 02, 2005 user's manual www.renesas.com before using this material, please visit our website to confirm that this is the most current document available. rej09b0193-0201
keep safety first in your circuit designs! notes regarding these materials 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with ap- propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non- flammable material or (iii) prevention against any malfunction or mishap. 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, pro- grams, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, pro- grams and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvements or other reasons. it is therefore recommended that customers con- tact renesas technology corp. or an authorized renesas technology corp. product dis- tributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corp. by vari- ous means, including the renesas technology corp. semiconductor home page (http:// www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all informa- tion as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liabil- ity or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or repro- duce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be im- ported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/ or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein.
revision history rev. date description page summary 4502 group user?s manual 1.00 oct 09, 2002 e first edition issued 2.00 aug 27, 2004 all pages words standardized: on-chip oscillator, a/d converter 1-4 ta=25?c added. 1-5 ____________ description of reset pin revised. 1-24 fig.20 : some description added. 1-26 fig.22 : note 5 added. 1-30 some description revised. 1-31 fig.25 : di instruction added. 1-32 table 11: revised. 1-41 table 15 : port level revised, note 6 added. 1-50 fig.49 : some description added. 1-51 note on power source voltage added. 2-43 table 2.7.1 : port level revised, note 6 added. 3-8 some description added. 3-30 fig.3.3.3 : some description revised. 3-35 note on power source voltage added. 2.01 feb 02, 2005 1-2 package name revised. 1-4 package name revised. 1-29 timer 1 and timer 2 count start timing and count time when operation starts added. 1-49 timer 1 and timer 2 count start timing and count time when operation starts added. 1-104 package name revised. 1-105 package name revised. 2-33 (6) timer 1 and timer 2 count start timing and count time when operation starts added. 3-31 (6) timer 1 and timer 2 count start timing and count time when operation starts added. 3-42 package outline revised.
this user? manual consists of the following three chapters. refer to the chapter appropriate to your conditions, such as hardware design or software development. 1. organization chapter 1 hardware this chapter describes features of the microcomputer and operation of each peripheral function. chapter 2 application this chapter describes usage and application examples of peripheral functions, based mainly on setting examples of related registers. chapter 3 appendix this chapter includes necessary information for systems development using the microcomputer, such as the electrical characteristics, the list of registers. as for the mask rom confirmation form, the rom programming confirmation form, and the mark specification form which are to be submitted when ordering, refer to the ?enesas technology corp.?hompage (http:/ /www.renesas.com/en/rom). as for the development tools and related documents, refer to the software and tools (http://www.renesas.com/ en/tools) of ?enesas technology corp.?homepage. before using this user? manual
4502 group i rev.2.01 feb 02, 2005 rej09b0193-0201 table of contents chapter 1 hardware description ............................................................................................................................... . 1-2 features ............................................................................................................................... ....... 1-2 application ............................................................................................................................... . 1-2 pin configuration .................................................................................................................. 1-2 block diagram ......................................................................................................................... 1-3 performance overview ....................................................................................................... 1-4 pin description ........................................................................................................................ 1-5 multifunction ..................................................................................................................... 1-5 port function .................................................................................................................... 1-6 definition of clock and cycle ................................................................................. 1-6 connections of unused pins ..................................................................................... 1-7 port block diagrams ..................................................................................................... 1-8 function block operations ........................................................................................... 1-13 cpu ............................................................................................................................ .............. 1-13 program memoy (rom) .................................................................................................. 1-16 data memory (ram) ......................................................................................................... 1-17 interrupt function ....................................................................................................... 1-18 external interrupts .................................................................................................... 1-22 timers ............................................................................................................................... .... 1-25 watchdog timer .............................................................................................................. 1-30 a/d converter .................................................................................................................. 1-32 reset function ................................................................................................................ 1-37 voltage drop detection circuit ........................................................................... 1-40 ram back-up mode .......................................................................................................... 1-41 clock control ................................................................................................................. 1-46 rom ordering method ....................................................................................................... 1-48 list of precautions ............................................................................................................ 1-49 control registers .............................................................................................................. 1-52 instructions ............................................................................................................................ 1-5 6 symbol ............................................................................................................................... ... 1-56 index list of instruction function ..................................................................... 1-57 machine instructions (index by alphabet) ....................................................... 1-61 machine instructions (index by types) .............................................................. 1-90 instruction code table ............................................................................................ 1-102 built-in prom version ...................................................................................................... 1-104 table of contents
4502 group ii rej09b0193-0201 rev.2.01 feb 02, 2005 chapter 2 application 2.1 i/o pins ............................................................................................................................... ..... 2-2 2.1.1 i/o ports .......................................................................................................................... 2-2 2.1.2 related registers ............................................................................................................ 2-6 2.1.3 port application examples ........................................................................................... 2-10 2.1.4 notes on use ................................................................................................................ 2-11 2.2 interrupts ............................................................................................................................... 2-13 2.2.1 interrupt functions ........................................................................................................ 2-13 2.2.2 related registers .......................................................................................................... 2-14 2.2.3 interrupt application examples .................................................................................... 2-17 2.2.4 notes on use ................................................................................................................ 2-21 2.3 timers ............................................................................................................................... ..... 2-22 2.3.1 timer functions .......................................................................................................... ... 2-22 2.3.2 related registers .......................................................................................................... 2-23 2.3.3 timer application examples ........................................................................................ 2-25 2.3.4 notes on use ................................................................................................................ 2-32 2.4 a/d converter ....................................................................................................................... 2-34 2.4.1 related registers .......................................................................................................... 2-35 2.4.2 a/d converter application examples .......................................................................... 2-35 2.4.3 notes on use ................................................................................................................ 2-37 2.5 reset ............................................................................................................................... ........ 2-39 2.5.1 reset circuit .................................................................................................................. 2-39 2.5.2 internal state at reset .................................................................................................. 2-40 2.5.3 notes on use ................................................................................................................ 2-41 2.6 voltage drop detection circuit .......................................................................................... 2-42 2.7 ram back-up ........................................................................................................................ 2-43 2.7.1 ram back-up mode ..................................................................................................... 2-43 2.7.2 related registers .......................................................................................................... 2-45 2.7.3 notes on use ................................................................................................................ 2-49 2.8 oscillation circuit ................................................................................................................ 2-50 2.8.1 oscillation circuit .......................................................................................................... 2-50 2.8.2 oscillation operation .................................................................................................... 2-52 2.8.3 notes on use ................................................................................................................ 2-53 table of contents
4502 group iii rev.2.01 feb 02, 2005 rej09b0193-0201 chapter 3 appendix 3.1 electrical characteristics ..................................................................................................... 3-2 3.1.1 absolute maximum ratings ............................................................................................ 3-2 3.1.2 recommended operating conditions ............................................................................ 3-3 3.1.3 electrical characteristics ................................................................................................ 3-5 3.1.4 a/d converter recommended operating conditions .................................................... 3-6 3.1.5 voltage drop detection circuit characteristics ............................................................. 3-7 3.1.6 basic timing diagram ..................................................................................................... 3-7 3.2 typical characteristics ......................................................................................................... 3-8 3.2.1 v dd ? dd characteristics ................................................................................................... 3-8 3.2.2 frequency characteristics ............................................................................................ 3-12 3.2.3 v ol ? ol characteristics (v dd = 5 v) ............................................................................ 3-14 3.2.4 input threshold (v ih ? il ) characteristics (ta = 25 ?) ............................................ 3-17 3.2.5 v dd ? pu characteristics (ports p0?2, d 2 /c, d 3 /k, reset) .................................. 3-20 3.2.6 analog input current characteristics pins v ain ? ain ................................................... 3-21 3.2.7 a/d converter operation current (v dd ?i dd ) characteristics (ta = 25 ?) ............ 3-23 3.2.8 voltage drop detection circuit characteristics ........................................................... 3-23 3.2.9 a/d converter typical characteristics ......................................................................... 3-25 3.3 list of precautions .............................................................................................................. 3-27 3.3.1 program counter ........................................................................................................... 3-27 3.3.2 stack registers (sks) and stack pointer (sp) .......................................................... 3-27 3.3.3 notes on i/o port ......................................................................................................... 3-27 3.3.4 notes on interrupt ........................................................................................................ 3-29 3.3.5 notes on timer .............................................................................................................. 3-31 3.3.6 notes on a/d conversion ............................................................................................ 3-32 3.3.7 notes on reset .............................................................................................................. 3-33 3.3.8 notes on ram back-up ............................................................................................... 3-34 3.3.9 notes on oscillation control ........................................................................................ 3-35 3.3.10 electric characteristic differences between mask rom and one time prom version mcu ... 3-35 3.3.11 notes on power source voltage ............................................................................. 3-35 3.4 notes on noise ..................................................................................................................... 3-36 3.4.1 shortest wiring length .................................................................................................. 3-36 3.4.2 connection of bypass capacitor across v ss line and v dd line ............................... 3-38 3.4.3 wiring to analog input pins ......................................................................................... 3-39 3.4.4 oscillator concerns ....................................................................................................... 3-39 3.4.5 setup for i/o ports ....................................................................................................... 3-40 3.4.6 providing of watchdog timer function by software ................................................... 3-40 3.5 package outline ................................................................................................................... 3-42 table of contents
4502 group iv rej09b0193-0201 rev.2.01 feb 02, 2005 list of figures chapter 1 hardware pin configuration (top view) (4502 group) ................................................................................. 1-2 block diagram (4502 group) ........................................................................................................ 1-3 port block diagram (1) ................................................................................................................... 1-8 port block diagram (2) ................................................................................................................... 1-9 port block diagram (3) ................................................................................................................. 1-10 port block diagram (4) ................................................................................................................. 1-11 external interrupt circuit structure .............................................................................................. 1-12 fig. 1 amc instruction execution example ............................................................................... 1-13 fig. 2 rar instruction execution example ............................................................................... 1-13 fig. 3 registers a, b and register e ........................................................................................ 1-13 fig. 4 tabp p instruction execution example .......................................................................... 1-13 fig. 5 stack registers (sks) structure ....................................................................................... 1-14 fig. 6 example of operation at subroutine call ....................................................................... 1-14 fig. 7 program counter (pc) structure ..................................................................................... 1-15 fig. 8 data pointer (dp) structure ............................................................................................. 1-15 fig. 9 sd instruction execution example .................................................................................. 1-15 fig. 10 rom map of m34502m4/m34502e4 ............................................................................ 1-16 fig. 11 page 1 (addresses 0080 16 to 00ff 16 ) structure ......................................................... 1-16 fig. 12 ram map ......................................................................................................................... 1-17 fig. 13 program example of interrupt processing ................................................................... 1-19 fig. 14 internal state when interrupt occurs ............................................................................ 1-19 fig. 15 interrupt system diagram ............................................................................................... 1-19 fig. 16 interrupt sequence .......................................................................................................... 1-21 fig. 17 external interrupt circuit structure ................................................................................ 1-22 fig. 18 external 0 interrupt program example-1 ...................................................................... 1-24 fig. 19 external 0 interrupt program example-2 ...................................................................... 1-24 fig. 20 external 0 interrupt program example-3 ...................................................................... 1-24 fig. 21 auto-reload function ....................................................................................................... 1-25 fig. 22 timers structure .............................................................................................................. 1-26 fig. 23 count timing diagram at cntr input .......................................................................... 1-29 fig. 24 timer count start timing and count time when operation starts (t1, t2) ............... 1-29 fig. 25 watchdog timer function ................................................................................................ 1-30 fig. 26 program example to start/stop watchdog timer ......................................................... 1-31 fig. 27 program example to enter the ram back-up mode when using the watchdog timer .... 1-31 fig. 28 a/d conversion circuit structure ................................................................................... 1-32 fig. 29 a/d conversion timing chart .......................................................................................... 1-34 fig. 30 setting registers .............................................................................................................. 1-34 fig. 31 comparator operation timing chart ............................................................................... 1-35 fig. 32 definition of a/d conversion accuracy ........................................................................ 1-36 fig. 33 reset release timing ...................................................................................................... 1-37 ____________ fig. 34 reset pin input waveform and reset operation ....................................................... 1-37 fig. 35 structure of reset pin and its peripherals, and power-on reset operation ............. 1-38 fig. 36 internal state at reset .................................................................................................... 1-39 fig. 37 voltage drop detection circuit ....................................................................................... 1-40 fig. 38 voltage drop detection circuit operation waveform example .................................... 1-40 fig. 39 state transition ................................................................................................................ 1-43 fig. 40 set source and clear source of the p flag ................................................................. 1-43 list of figures
4502 group v rev.2.01 feb 02, 2005 rej09b0193-0201 list of figures fig. 41 start condition identified example using the snzp instruction ................................ 1-43 fig. 42 clock control circuit structure ....................................................................................... 1-46 fig. 43 switch to ceramic resonance/rc oscillation ............................................................... 1-47 fig. 44 handling of x in and x out when operating on-chip oscillator .................................... 1-47 fig. 45 ceramic resonator external circuit ............................................................................... 1-47 fig. 46 external rc oscillation circuit ....................................................................................... 1-47 fig. 47 external clock input circuit ............................................................................................ 1-48 fig. 48 timer count start timing and count time when operation starts (t1, t2) ............... 1-49 fig. 49 external 0 interrupt program example-1 ...................................................................... 1-50 fig. 50 external 0 interrupt program example-2 ...................................................................... 1-50 fig. 51 external 0 interrupt program example-3 ...................................................................... 1-50 fig. 52 a/d conversion interrupt program example ................................................................ 1-51 fig. 53 analog input external circuit example-1 ...................................................................... 1-51 fig. 54 analog input external circuit example-2 ...................................................................... 1-51 fig. 55 flow of writing and test of the product shipped in blank ....................................... 1-104 fig. 56 pin configuration of built-in prom version .............................................................. 1-105 chapter 2 application fig. 2.1.1 key input by key scan ............................................................................................... 2-10 fig. 2.1.2 key scan input timing ................................................................................................ 2-10 fig. 2.2.1 int interrupt operation example .............................................................................. 2-17 fig. 2.2.2 int interrupt setting example ................................................................................... 2-18 fig. 2.2.3 timer 1 constant period interrupt setting example ................................................ 2-19 fig. 2.2.4 timer 2 constant period interrupt setting example ................................................ 2-20 fig. 2.3.1 peripheral circuit example ......................................................................................... 2-25 fig. 2.3.2 watchdog timer function ............................................................................................ 2-26 fig. 2.3.3 constant period measurement setting example ..................................................... 2-27 fig. 2.3.4 cntr output setting example .................................................................................. 2-28 fig. 2.3.5 cntr input setting example ..................................................................................... 2-29 fig. 2.3.6 timer start by external input setting example (1) ................................................. 2-30 fig. 2.3.7 timer start by external input setting example (2) ................................................. 2-31 fig. 2.3.8 watchdog timer setting example .............................................................................. 2-32 fig. 2.3.9 timer count start timing and count time when operation starts (t1, t2) ................ 2-33 fig. 2.4.1 a/d converter structure ............................................................................................. 2-34 fig. 2.4.2 a/d conversion mode setting example .................................................................... 2-36 fig. 2.4.3 analog input external circuit example-1 .................................................................. 2-37 fig. 2.4.4 analog input external circuit example-2 .................................................................. 2-37 fig. 2.4.5 a/d converter operating mode program example .................................................. 2-37 fig. 2.5.1 structure of reset pin and its peripherals, and power-on reset operation ......... 2-39 fig. 2.5.2 oscillation stabilizing time after system is released from reset .......................... 2-39 fig. 2.5.3 internal state at reset ................................................................................................ 2-40 fig. 2.6.1 voltage drop detection circuit ................................................................................... 2-42 fig. 2.6.2 voltage drop detection circuit operation waveform example ............................... 2-42 fig. 2.7.1 start condition identified example ............................................................................ 2-44 fig. 2.8.1 switch to ceramic resonance/rc oscillation .......................................................... 2-50 fig. 2.8.2 handling of x in and x out when operating on-chip oscillator ................................ 2-50 fig. 2.8.3 ceramic resonator external circuit ........................................................................... 2-51 fig. 2.8.4 external rc oscillation circuit .................................................................................. 2-51 fig. 2.8.5 structure of clock control circuit .............................................................................. 2-52
4502 group vi rej09b0193-0201 rev.2.01 feb 02, 2005 list of figures chapter 3 appendix fig. 3.2.1 a/d conversion characteristics data ........................................................................ 3-25 fig. 3.3.1 external 0 interrupt program example-1 ................................................................. 3-29 fig. 3.3.2 external 0 interrupt program example-2 ................................................................. 3-30 fig. 3.3.3 external 0 interrupt program example-3 ................................................................. 3-30 fig. 3.3.4 timer count start timing and count time when operation starts (t1, t2) ................ 3-31 fig. 3.3.5 analog input external circuit example-1 .................................................................. 3-32 fig. 3.3.6 analog input external circuit example-2 .................................................................. 3-32 fig. 3.3.7 a/d converter operating mode program example .................................................. 3-32 fig. 3.4.1 selection of packages ............................................................................................... 3-36 fig. 3.4.2 wiring for the reset input pin ............................................................................... 3-36 fig. 3.4.3 wiring for clock i/o pins ........................................................................................... 3-37 fig. 3.4.4 wiring for cnv ss pin .................................................................................................. 3-37 fig. 3.4.5 wiring for the v pp pin of the built-in prom version ............................................. 3-38 fig. 3.4.6 bypass capacitor across the v ss line and the v dd line ........................................ 3-38 fig. 3.4.7 analog signal line and a resistor and a capacitor ................................................ 3-39 fig. 3.4.8 wiring for a large current signal line ...................................................................... 3-39 fig. 3.4.9 wiring to a signal line where potential levels change frequently ....................... 3-40 fig. 3.4.10 v ss pattern on the underside of an oscillator ...................................................... 3-40 fig. 3.4.11 watchdog timer by software ................................................................................... 3-41
4502 group vii rev.2.01 feb 02, 2005 rej09b0193-0201 list of tables chapter 1 hardware table selection of system clock .................................................................................................. 1-6 table 1 rom size and pages .................................................................................................... 1-16 table 2 ram size ........................................................................................................................ 1-17 table 3 interrupt sources ............................................................................................................ 1-18 table 4 interrupt request flag, interrupt enable bit and skip instruction .............................. 1-18 table 5 interrupt enable bit function ......................................................................................... 1-18 table 6 interrupt control registers ............................................................................................. 1-20 table 7 external interrupt activated conditions ........................................................................ 1-22 table 8 external interrupt control register ................................................................................ 1-23 table 9 function related timers ................................................................................................. 1-25 table 10 timer control registers ................................................................................................ 1-27 table 11 a/d converter characteristics ..................................................................................... 1-32 table 12 a/d control registers ................................................................................................... 1-33 table 13 change of successive comparison register ad during a/d conversion .............. 1-34 table 14 port state at reset ....................................................................................................... 1-38 table 15 functions and states retained at ram back-up ..................................................... 1-41 table 16 return source and return condition .......................................................................... 1-42 table 17 key-on wakeup control register ................................................................................. 1-44 table 18 pull-up control register and interrupt control register ............................................ 1-45 table 19 clock control register mr .......................................................................................... 1-48 table 20 product of built-in prom version ........................................................................... 1-104 chapter 2 application table 2.1.1 key-on wakeup control register k0 ........................................................................ 2-6 table 2.1.2 pull-up control register pu0 .................................................................................... 2-6 table 2.1.3 key-on wakeup control register k1 ........................................................................ 2-7 table 2.1.4 pull-up control register pu1 .................................................................................... 2-7 table 2.1.5 key-on wakeup control register k2 ........................................................................ 2-8 table 2.1.6 pull-up control register pu2 .................................................................................... 2-8 table 2.1.7 timer control register w6 ........................................................................................ 2-9 table 2.1.8 connections of unused pins ................................................................................... 2-12 table 2.2.1 interrupt control register v1 ................................................................................... 2-14 table 2.2.2 interrupt control register v2 ................................................................................... 2-15 table 2.2.3 interrupt control register i1 .................................................................................... 2-16 table 2.3.1 interrupt control register v1 ................................................................................... 2-23 table 2.3.2 timer control register w1 ...................................................................................... 2-23 table 2.3.3 timer control register w2 ...................................................................................... 2-24 table 2.3.4 timer control register w6 ...................................................................................... 2-24 table 2.3.5 recommended operating condition of pulse width input to cntr pin ........... 2-33 table 2.4.1 a/d control register q1 .......................................................................................... 2-35 table 2.4.2 recommended operating conditions (when using a/d converter) ................... 2-38 list of tables
4502 group viii rej09b0193-0201 rev.2.01 feb 02, 2005 list of tables table 2.7.1 functions and states retained at ram back-up mode ...................................... 2-43 table 2.7.2 return source and return condition ...................................................................... 2-44 table 2.7.3 start condition identification ................................................................................... 2-44 table 2.7.4 key-on wakeup control register k0 ...................................................................... 2-45 table 2.7.5 pull-up control register pu0 .................................................................................. 2-45 table 2.7.6 key-on wakeup control register k1 ...................................................................... 2-46 table 2.7.7 pull-up control register pu1 .................................................................................. 2-46 table 2.7.8 key-on wakeup control register k2 ...................................................................... 2-47 table 2.7.9 pull-up control register pu2 .................................................................................. 2-47 table 2.7.10 interrupt control register i1 .................................................................................. 2-48 table 2.8.1 maximum value of oscillation frequency and supply voltage ............................ 2-51 chapter 3 appendix table 3.1.1 absolute maximum ratings ....................................................................................... 3-2 table 3.1.2 recommended operating conditions 1 ................................................................... 3-3 table 3.1.3 recommended operating conditions 2 ................................................................... 3-4 table 3.1.4 electrical characteristics ........................................................................................... 3-5 table 3.1.5 a/d converter recommended operating conditions ............................................... 3-6 table 3.1.6 a/d converter characteristcs .................................................................................... 3-6 table 3.1.7 voltage drop detection circuit characteristics ........................................................ 3-7 table 3.3.1 connections of unused pins .................................................................................. 3-28 table 3.3.2 recommended operating condition of pulse width input to cntr pin ........... 3-31 table 3.3.3 recommended operating conditions (when using a/d converter) ................... 3-33
chapter 1 hardware description features application pin configuration block diagram performance overview pin description function block operations rom ordering method list of precautions control registers instructions built-in prom version
1-2 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 description the 4502 group is a 4-bit single-chip microcomputer designed with cmos technology. its cpu is that of the 4500 series using a simple, high-speed instruction set. the computer is equipped with two 8-bit timers (each timer has a reload register), interrupts, and 10-bit a/d converter. the various microcomputers in the 4502 group include variations of the built-in memory size as shown in the table below. features minimum instruction execution time ................................ 0.68 s (at 4.4 mhz oscillation frequency, in high-speed mode) supply voltage ............................................................. 2.7 to 5.5 v (system is in the reset state when the voltage is under the detec- tion voltage of voltage drop detection circuit) part number M34502M2-XXXFP m34502m4-xxxfp m34502e4fp ( note ) rom type mask rom mask rom one time prom package prsp0024ga-a prsp0024ga-a prsp0024ga-a ram size ( ? 4 bits) 128 words 256 words 256 words rom (prom) size ( ? 10 bits) 2048 words 4096 words 4096 words timers timer 1 ...................................... 8-bit timer with a reload register timer 2 ...................................... 8-bit timer with a reload register interrupt ........................................................................ 4 sources key-on wakeup function pins ................................................... 12 input/output port ...................................................................... 18 a/d converter .................. 10-bit successive comparison method watchdog timer clock generating circuit (ceramic resonator/rc oscillation) led drive directly enabled (port d) power-on reset circuit voltage drop detection circuit ........................... vrst: typ. 3.5 v (ta = 25 ?) application electrical household appliance, consumer electronic products, of- fice automation equipment, etc. note: shipped in blank. description/features/application/pin configuration pin configuration 1 7 18 2 1 2 0 2 2 1 9 23 24 1 6 1 5 14 13 v d d p1 0 p 1 1 p 1 2 / c n t r p 1 3 / i n t p 0 3 p 0 2 p0 1 p 0 0 v s s d 4 d 5 x i n x out c n v s s p2 1 /a in1 p 2 0 / a i n 0 m 3 4 5 0 2 r e s e t d 2 / c d 3 / k d 1 d 0 p 3 1 / a i n 3 p 3 0 / a i n 2 outline prsp0024ga-a (24p2q-a ) m 3 4 5 0 2 m x - x x x f p m 3 4 5 0 2 e 4 f p 8 7 4 5 3 6 2 1 9 1 0 11 1 2 pin configuration (top view) (4502 group)
1-3 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 block diagram (4502 group) r a m r o m m e m o r y i / o p o r t i n t e r n a l p e r i p h e r a l f u n c t i o n s t i m e r t i m e r 1 ( 8 b i t s ) s y s t e m c l o c k g e n e r a t i n g c i r c u i t t i m e r 2 ( 8 b i t s ) 1 2 8 , 2 5 6 w o r d s ? ? ?
1-4 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 performance overview function 113 0.68 ? ? ? ? a in3 is also used as ports p2 0 , p2 1 , p3 0 , p3 1 , respectively. 8-bit programmable timer with a reload register. 8-bit programmable timer with a reload register and has a event counter. 10-bit wide, this is equipped with an 8-bit comparator function. 4 channel (a in0 pin a in3 pin) 4 (one for external, two for timer, one for a/d) 1 level 8 levels cmos silicon gate 24-pin plastic molded ssop (prsp0024ga-a) 20 c to 85 c 2.7 to 5.5 v (system is in the reset state when the voltage is under the detection voltage of voltage drop detection circuit) 1.7 ma (ta=25 c, v dd = 5.0 v, 4.0 mhz oscillation frequency, in high-speed mode, output tran- sistors in the cut-off state) 0.1 c, v dd = 5 v, output transistors in the cut-off state) parameter number of basic instructions minimum instruction execution time memory sizes input/output ports rom ram d 0 d 5 p0 0 p0 3 p1 0 p1 3 p2 0 , p2 1 p3 0 , p3 1 c k cntr int a in0 , a in1 a in2 , a in3 timer 1 timer 2 analog input sources nesting active mode ram back-up mode m34502m2 m34502m4/e4 m34502m2 m34502m4/e4 i/o i/o i/o i/o i/o i/o i/o timer i/o interrupt input analog input timers a/d converter interrupt subroutine nesting device structure package operating temperature range supply voltage power dissipation (typical value) performance overview
1-5 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 pin description name power supply ground cnv ss reset input/output system clock input i/o port d i/o port p0 i/o port p1 i/o port p2 i/o port p3 i/o port c i/o port k timer input/output interrupt input analog input pin v dd v ss cnv ss reset x in d 0 d 5 p0 0 p0 3 p1 0 p1 3 p2 0 , p2 1 p3 0 , p3 1 port c port k cntr int a in0 a in3 input/output i/o input i/o i/o i/o i/o i/o i/o i/o i/o input input function connected to a plus power supply. connected to a 0 v power supply. connect cnv ss to v ss and apply l (0v) to cnv ss certainly. an n-channel open-drain i/o pin for a system reset. when the watchdog timer, the built-in power-on reset or the voltage drop detection circuit causes the system to be reset, the reset pin outputs l level. i/o pins of the system clock generating circuit. when using a ceramic resonator, connect it between pins x in and x out . a feedback resistor is built-in between them. when using the rc oscillation, connect a resistor and a capacitor to x in , and leave x out pin open. each pin of port d has an independent 1-bit wide i/o function. each pin has an out- put latch. for input use, set the latch of the specified bit to 1. input is examined by skip decision. the output structure is n-channel open-drain. ports d 2 and d 3 are equipped with a pull-up function and a key-on wakeup function. both functions can be switched by software. ports d 2 and d 3 are also used as ports c and k, respectively. p ort p0 serves as a 4-bit i/o port, and it can be used as inputs when the output latch is set to 1. the output structure is n-channel open-drain. port p0 has a key-on wakeup function and a pull-up function. both functions can be switched by software. p ort p1 serves as a 4-bit i/o port, and it can be used as inputs when the output latch is set to 1. the output structure is n-channel open-drain. port p1 has a key-on wakeup function and a pull-up function. both functions can be switched by software. ports p1 2 and p1 3 are also used as cntr and int, respectively. p ort p2 serves as a 2-bit i/o port, and it can be used as inputs when the output latch is set to 1. the output structure is n-channel open-drain. port p2 has a key-on wakeup function and a pull-up function. both functions can be switched by software. ports p2 0 and p2 1 are also used as a in0 and a in1 , respectively. p ort p3 serves as a 2-bit i/o port, and it can be used as inputs when the output latch is set to 1. the output structure is n-channel open-drain. ports p3 0 and p3 1 are also used as a in2 and a in3 , respectively. 1 -bit i/o port. port c can be used as inputs when the output latch is set to 1. the output structure is n-channel open-drain. port c has a key-on wakeup function and a pull-up function. both functions can be switched by software. port c is also used as port d 2 . 1 -bit i/o port. port k can be used as inputs when the output latch is set to 1. the output structure is n-channel open-drain. port k has a key-on wakeup function and a pull-up function. both functions can be switched by software. port k is also used as port d 3 . cntr pin has the function to input the clock for the timer 2 event counter, and to out- put the timer 1 or timer 2 underflow signal divided by 2. this pin is also used as port p1 2 . int pin accepts external interrupts. it has the key-on wakeup function which can be switched by software. this pin is also used as port p1 3 . a/d converter analog input pins. a in0 and a in1 are also used as ports p2 0 and p2 1 , respectively. a in2 and a in3 are also used as ports p3 0 and p3 1 , respectively. notes 1: pins except above have just single function. 2: the input/output of d 2 , d 3 , p1 2 and p1 3 can be used even when c, k, cntr (input) and int are selected. 3: the input of p1 2 can be used even when cntr (output) is selected. 4: the input/output of p2 0 , p2 1 , p3 0 and p3 1 can be used even when a in0 , a in1 , a in2 and a in3 are selected. pin d 2 d 3 p1 2 p1 3 multifunction c k cntr int multifunction pin c k cntr int multifunction d 2 d 3 p1 2 p1 3 pin p2 0 p2 1 p3 0 p3 1 multifunction a in0 a in1 a in2 a in3 pin a in0 a in1 a in2 a in3 multifunction p2 0 p2 1 p3 0 p3 1 x out system clock output output pin description
1-6 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 definition of clock and cycle external ceramic resonator external rc oscillation clock (f(x in )) by the external clock clock (f(ring)) of the on-chip oscillator which is the internal oscillator.] table selection of system clock notes 1: the on-chip oscillator clock is f(ring), the clock by the ceramic resonator, rc oscillation or external clock is f(x in ). 2: the default mode is selected after system is released from reset and is returned from ram back-up. mr 2 0 1 0 1 mr 3 0 0 1 1 operation mode high-speed mode middle-speed mode low-speed mode default mode port function port port d port p0 port p1 port p2 port p3 i/o unit 1 4 4 2 2 control instructions sd, rd szd, cld scp, rcp snzcp iak, oka op0a iap0 op1a iap1 op2a iap2 op3a iap3 control registers pu2, k2 pu0, k0 pu1, k1 w6, i1 pu2, k2 q1 q1 output structure n-channel open-drain n-channel open-drain n-channel open-drain n-channel open-drain n-channel open-drain input output i/o (6) i/o (4) i/o (4) i/o (2) i/o (2) remark pin d 0 , d 1 , d 4 , d 5 d 2 /c d 3 /k p0 0 p0 3 p1 0 , p1 1 p1 2 /cntr, p1 3 /int p2 0 /a in0 p2 1 /a in1 p3 0 /a in2 p3 1 /a in3 built-in programmable pull-up functions key-on wakeup functions (programmable) built-in programmable pull-up functions key-on wakeup functions (programmable) built-in programmable pull-up functions key-on wakeup functions (programmable) built-in programmable pull-up functions key-on wakeup functions (programmable) pin description
1-7 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 notes 1: when the ceramic resonator or the rc oscillation is not selected by program, system operates by the on-chip oscillator (internal oscillator). 2: when the pull-up function is left valid, the supply current is increased. do not select the pull-up function. 3: when the key-on wakeup function is left valid, the system returns from the ram back-up state immediately after going into th e ram back-up state. do not select the key-on wakeup function. 4: when selecting the key-on wakeup function, select also the pull-up function. 5: clear the bit 3 (i1 3 ) of register i1 to 0 to disable to input to int pin (after reset: i1 3 = 0 ) (note when connecting to v ss ) connections of unused pins connection connect to v ss . open. open. (output latch is set to 1. ) open. (output latch is set to 0. ) connect to v ss . open. (output latch is set to 1. ) open. (output latch is set to 0. ) connect to v ss . open. (output latch is set to 1. ) open. (output latch is set to 0. ) connect to v ss . open. (output latch is set to 1. ) open. (output latch is set to 0. ) connect to v ss . open. (output latch is set to 1. ) open. (output latch is set to 0. ) connect to v ss . open. (output latch is set to 1. ) open. (output latch is set to 0. ) connect to v ss . open. (output latch is set to 1. ) open. (output latch is set to 0. ) connect to v ss . pin x in x out d 0 , d 1 d 4 , d 5 d 2 /c d 3 /k p0 0 p0 3 p1 0 , p1 1 p1 2 /cntr p1 3 /int p2 0 /a in0 p2 1 /a in1 p3 0 /a in2 p3 1 /a in3 usage condition system operates by the on-chip oscillator. (note 1) system operates by the external clock. (the ceramic resonator is selected with the cmck instruction.) system operates by the rc oscillator. (the rc oscillation is selected with the crck instruction.) system operates by the on-chip oscillator. (note 1) the key-on wakeup function is not selected. (note 4) the pull-up function and the key-on wakeup function are not selected. (notes 2, 3) the pull-up function and the key-on wakeup function are not selected. (notes 2, 3) the key-on wakeup function is not selected. (note 4) the pull-up function and the key-on wakeup function are not selected. (notes 2, 3) the pull-up function and the key-on wakeup function are not selected. (notes 2, 3) the key-on wakeup function is not selected. (note 4) the pull-up function and the key-on wakeup function are not selected. (notes 2, 3) the pull-up function and the key-on wakeup function are not selected. (notes 2, 3) the key-on wakeup function is not selected. the input to int pin is disabled. (notes 4, 5) the pull-up function and the key-on wakeup function are not selected. (notes 2, 3) the pull-up function and the key-on wakeup function are not selected. (notes 2, 3) the key-on wakeup function is not selected. (note 4) the pull-up function and the key-on wakeup function are not selected. (notes 2, 3) the pull-up function and the key-on wakeup function are not selected. (notes 2, 3) pin description
1-8 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 port block diagrams d 0 , d 1 , d 4 , d 5 s rq (note 1) d 2 / c s rq skip decision (szd instruction) (note 1) pu2 2 s rq k2 2 pull-up transistor ( n o t e 2 ) l level detection circuit d 3 /k s rq pu2 3 d tq a 0 o k a i n s t r u c t i o n register a iak instruction k 2 3 ( n o t e 2 ) sd instruction d e c o d e r skip decision (szd instruction) r e g i s t e r y r d i n s t r u c t i o n cld instruction skip decision (snzcp instruction) sd instruction r d i n s t r u c t i o n c l d i n s t r u c t i o n d e c o d e r r e g i s t e r y scp instruction rcp instruction key-on wakeup skip decision (szd instruction) (note 1) pull-up transistor l level detection circuit sd instruction r d i n s t r u c t i o n c l d i n s t r u c t i o n decoder register y k e y - o n w a k e u p this symbol represents a parasitic diode on the port. 2: applied potential to ports d 2 /c and d 3 /k must be v dd or less. n o t e s 1 : port block diagram (1) pin description
1-9 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 port block diagram (2) i a p 0 i n s t r u c t i o n k0 i o p 0 a i n s t r u c t i o n r e g i s t e r a a i a i d t q ( n o t e 1 ) pu0 i ( n o t e 2 ) ( n o t e 2 ) ( n o t e 4 ) l l e v e l d e t e c t i o n c i r c u i t p 0 2 , p 0 3 iap0 instruction k0 j o p 0 a i n s t r u c t i o n r e g i s t e r a a j a j d t q ( n o t e 1 ) pu0 j p u l l - u p t r a n s i s t o r ( n o t e 3 ) ( n o t e 3 ) (note 4) k e y - o n w a k e u p l level detection circuit t h i s s y m b o l r e p r e s e n t s a p a r a s i t i c d i o d e o n t h e p o r t . 2 : i r e p r e s e n t s 0 o r 1 . 3 : j r e p r e s e n t s 2 o r 3 . 4 : a p p l i e d p o t e n t i a l t o p o r t p 0 m u s t b e v d d o r l e s s . notes 1: k e y - o n w a k e u p i n p u t p u l l - u p t r a n s i s t o r p 0 0 , p 0 1 pin description
1-10 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 port block diagram (3) p1 0 , p1 1 (note 3) register a a i ai d tq ( n o t e 2 ) k1 i pu1 i (note 2) ( n o t e 2 ) a 3 a 3 d t q pu1 3 p1 3 /int (note 3) k1 3 k 1 3 p 1 2 / c n t r ( n o t e 3 ) a 2 a 2 d tq k1 2 pu1 2 w6 0 0 1 w 2 0 w 2 1 i a p 1 i n s t r u c t i o n o p 1 a i n s t r u c t i o n ( n o t e 1 ) l level detection circuit t h i s s y m b o l r e p r e s e n t s a p a r a s i t i c d i o d e o n t h e p o r t . 2 : i r e p r e s e n t s 0 o r 1 . 3 : a p p l i e d p o t e n t i a l t o p o r t p 1 m u s t b e v d d o r l e s s . n o t e s 1 : k e y - o n w a k e u p i n p u t pull-up transistor r e g i s t e r a iap1 instruction op1a instruction (note 1) l l e v e l d e t e c t i o n c i r c u i t k e y - o n w a k e u p i n p u t pull-up transistor clock input for timer 2 event counter t i m e r 1 o r t i m e r 2 u n d e r f l o w s i g n a l d i v i d e d b y 2 l l e v e l d e t e c t i o n c i r c u i t key-on wakeup input p u l l - u p t r a n s i s t o r r e g i s t e r a i a p 1 i n s t r u c t i o n o p 1 a i n s t r u c t i o n e x t e r n a l 0 i n t e r r u p te x t e r n a l i n t e r r u p t c i r c u i t (note 1) pin description
1-11 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 port block diagram (4) a 1 a 1 d t q pu2 1 p2 1 /a in1 k2 1 a i a i d t q ( n o t e 1 ) ( n o t e 3 ) p3 0 /a in2 , p3 1 /a in3 decoder analog input q1 ( n o t e 2 ) a 0 a 0 d t q ( n o t e 3 ) p u 2 0 p2 0 /a in0 k 2 0 a n a l o g i n p u t r e g i s t e r a i a p 2 i n s t r u c t i o n op2a instruction (note 1) l l e v e l d e t e c t i o n c i r c u i t k e y - o n w a k e u p i n p u t p u l l - u p t r a n s i s t o r decoder register a i a p 2 i n s t r u c t i o n o p 2 a i n s t r u c t i o n (note 1) l level detection circuit key-on wakeup input p u l l - u p t r a n s i s t o r (note 3) a n a l o g i n p u t d e c o d e r r e g i s t e r a i a p 3 i n s t r u c t i o n o p 3 a i n s t r u c t i o n this symbol represents a parasitic diode on the port. 2: i represents 0 or 1. 3: applied potential to ports p2 and p3 must be v dd or less. notes 1: q1 q1 pin description
1-12 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 external interrupt circuit structure 0 1 i1 2 0 1 e x f 0 i 1 1 s n z i 0 i n s t r u c t i o n p 1 3 / i n t k 1 3 i 1 3 (note) wakeup skip r i s i n g f a l l i n g o n e - s i d e d e d g e d e t e c t i o n c i r c u i t b o t h e d g e s d e t e c t i o n c i r c u i t e x t e r n a l 0 i n t e r r u p t this symbol represents a parasitic diode on the port. timer 1 count start synchronization circuit input pin description
1-13 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 function block operations cpu (1) arithmetic logic unit (alu) the arithmetic logic unit alu performs 4-bit arithmetic such as 4- bit data addition, comparison, and operation, or operation, and bit manipulation. (2) register a and carry flag register a is a 4-bit register used for arithmetic, transfer, ex- change, and i/o operation. carry flag cy is a 1-bit flag that is set to 1 when there is a carry with the amc instruction (figure 1). it is unchanged with both a n instruction and am instruction. the value of a 0 is stored in carry flag cy with the rar instruction (fig- ure 2). carry flag cy can be set to 1 with the sc instruction and cleared to 0 with the rc instruction. (3) registers b and e register b is a 4-bit register used for temporary storage of 4-bit data, and for 8-bit data transfer together with register a. register e is an 8-bit register. it can be used for 8-bit data transfer with register b used as the high-order 4 bits and register a as the low-order 4 bits (figure 3). register e is undefined after system is released from reset and re- turned from the ram back-up. accordingly, set the initial value. (4) register d register d is a 3-bit register. it is used to store a 7-bit rom address together with register a and is used as a pointer within the specified page when the tabp p, bla p, or bmla p instruction is executed (figure 4). register d is undefined after system is released from reset and re- turned from the ram back-up. accordingly, set the initial value. fig. 1 amc instruction execution example fig. 2 rar instruction execution example fig. 3 registers a, b and register e fig. 4 tabp p instruction execution example ( c y ) (m(dp)) ( a ) a d d i t i o n alu < c a r r y > < r e s u l t > a 3 a 2 a 1 a 0 b 3 b 2 b 1 b 0 e 7 e 6 e 5 e 4 e 3 e 2 e 1 e 0 a 3 a 2 a 1 a 0 b 3 b 2 b 1 b 0 t a b i n s t r u c t i o n t e a b i n s t r u c t i o n t a b e i n s t r u c t i o n tba instruction register b r e g i s t e r a register b register a register e c ya 3 a 2 a 1 a 0 a 0 c ya 3 a 2 a 1 rar instruction sc instruction < c l e a r > r c i n s t r u c t i o n s p e c i f y i n g a d d r e s s t a b p p i n s t r u c t i o n p 6 p 5 p 4 p 3 p 2 p 1 p 0 pc h dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 pc l i m m e d i a t e f i e l d v a l u e p the contents of register d rom 840 middle-order 4 bits l o w - o r d e r 4 b i t s register a (4) register b (4) the contents of register a function block operations
1-14 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 (5) stack registers (sk s ) and stack pointer (sp) stack registers (sks) are used to temporarily store the contents of program counter (pc) just before branching until returning to the original routine when; branching to an interrupt service routine (referred to as an inter- rupt service routine), performing a subroutine call, or executing the table reference instruction (tabp p). stack registers (sks) are eight identical registers, so that subrou- tines can be nested up to 8 levels. however, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. accordingly, be care- ful not to over the stack when performing these operations together. the contents of registers sks are destroyed when 8 lev- els are exceeded. the register sk nesting level is pointed automatically by 3-bit stack pointer (sp). the contents of the stack pointer (sp) can be transferred to register a with the tasp instruction. figure 5 shows the stack registers (sks) structure. figure 6 shows the example of operation at subroutine call. (6) interrupt stack register (sdp) interrupt stack register (sdp) is a 1-stage register. when an inter- rupt occurs, this register (sdp) is used to temporarily store the contents of data pointer, carry flag, skip flag, register a, and regis- ter b just before an interrupt until returning to the original routine. unlike the stack registers (sks), this register (sdp) is not used when executing the subroutine call instruction and the table refer- ence instruction. (7) skip flag skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. when an interrupt oc- curs, the contents of skip flag is stored automatically in the interrupt stack register (sdp) and the skip condition is retained. fig. 5 stack registers (sks) structure fig. 6 example of operation at subroutine call s k 0 s k 1 s k 2 s k 3 s k 4 s k 5 s k 6 sk 7 ( s p ) = 0 ( s p ) = 1 ( s p ) = 2 ( s p ) = 3 ( s p ) = 4 ( s p ) = 5 ( s p ) = 6 (sp) = 7 program counter (pc) e x e c u t i n g r t i n s t r u c t i o n e x e c u t i n g b m i n s t r u c t i o n s t a c k p o i n t e r ( s p ) p o i n t s 7 a t r e s e t o r r e t u r n i n g f r o m r a m b a c k - u p m o d e . i t p o i n t s 0 b y e x e c u t i n g t h e f i r s t b m i n s t r u c t i o n , a n d t h e c o n t e n t s o f p r o g r a m c o u n t e r i s s t o r e d i n s k 0 . w h e n t h e b m i n s t r u c t i o n i s e x e c u t e d a f t e r e i g h t s t a c k r e g i s t e r s a r e u s e d ( ( s p ) = 7 ) , ( s p ) = 0 a n d t h e c o n t e n t s o f s k 0 i s d e s t r o y e d . returning to the bm instruction execution address with the rt instruction, and the bm instruction becomes the nop instruction. (sp) note : function block operations
1-15 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 (8) program counter (pc) program counter (pc) is used to specify a rom address (page and address). it determines a sequence in which instructions stored in rom are read. it is a binary counter that increments the number of instruction bytes each time an instruction is executed. however, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table refer- ence instruction (tabp p) is executed. program counter consists of pc h (most significant bit to bit 7) which specifies to a rom page and pc l (bits 6 to 0) which speci- fies an address within a page. after it reaches the last address (address 127) of a page, it specifies address 0 of the next page (figure 7). make sure that the pc h does not specify after the last page of the built-in rom. (9) data pointer (dp) data pointer (dp) is used to specify a ram address and consists of registers z, x, and y. register z specifies a ram file group, reg- ister x specifies a file, and register y specifies a ram digit (figure 8). register y is also used to specify the port d bit position. when using port d, set the port d bit position to register y certainly and execute the sd, rd, or szd instruction (figure 9). note register z of data pointer is undefined after system is released from reset. also, registers z, x and y are undefined in the ram back-up. after system is returned from the ram back-up, set these registers. fig. 7 program counter (pc) structure fig. 8 data pointer (dp) structure fig. 9 sd instruction execution example p 5 p 4 p 3 p 2 p 1 p 0 a 6 a 5 a 4 a 3 a 2 a 1 a 0 p r o g r a m c o u n t e r p c h s p e c i f y i n g p a g e p c l s p e c i f y i n g a d d r e s s p 6 z 1 z 0 x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 d a t a p o i n t e r ( d p ) r e g i s t e r z ( 2 ) r e g i s t e r x ( 4 ) r e g i s t e r y ( 4 ) specifying ram digit specifying ram file specifying ram file group 0 01 1 s e t specifying bit position p o r t d o u t p u t l a t c h r e g i s t e r y ( 4 ) d 2 d 3 d 1 d 0 0 function block operations
1-16 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 program memoy (rom) the program memory is a mask rom. 1 word of rom is composed of 10 bits. rom is separated every 128 words by the unit of page (addresses 0 to 127). table 1 shows the rom size and pages. fig- ure 10 shows the rom map of m34502m4. table 1 rom size and pages part number m34502m2 m34502m4 m34502e4 rom (prom) size ( ? fig. 10 rom map of m34502m4/m34502e4 fig. 11 page 1 (addresses 0080 16 to 00ff 16 ) structure 0 87654321 0 0 0 0 1 6 0 0 8 0 1 6 0 1 7 f 1 6 s u b r o u t i n e s p e c i a l p a g e 0 0 7 f 1 6 0 0 f f 1 6 0 1 0 0 1 6 0 1 8 0 1 6 p a g e 1 p a g e 2 p a g e 0 p a g e 3 p a g e 3 1 0 f f f 1 6 interrupt address page 9 90 87654321 external 0 interrupt address 0080 16 0082 16 timer 1 interrupt address 0084 16 timer 2 interrupt address 0086 16 0088 16 0 0 8 a 1 6 0 0 f f 1 6 a/d interrupt address 008c 16 008e 16 function block operations
1-17 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 data memory (ram) 1 word of ram is composed of 4 bits, but 1-bit manipulation (with the sb j, rb j, and szb j instructions) is enabled for the entire memory area. a ram address is specified by a data pointer. the data pointer consists of registers z, x, and y. set a value to the data pointer certainly when executing an instruction to access ram. table 2 shows the ram size. figure 12 shows the ram map. note register z of data pointer is undefined after system is released from reset. also, registers z, x and y are undefined in the ram back-up. after system is returned from the ram back-up, set these registers. fig. 12 ram map table 2 ram size part number m34502m2 m34502m4 m34502e4 ram size 128 words ? ? ? ?
1-18 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 interrupt function the interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. an interrupt occurs when the following 3 conditions are satisfied. an interrupt activated condition is satisfied (request flag = 1 ) interrupt enable bit is enabled ( 1 ) interrupt enable flag is enabled (inte = 1 ) table 3 shows interrupt sources. (refer to each interrupt request flag for details of activated conditions.) (1) interrupt enable flag (inte) the interrupt enable flag (inte) controls whether the every inter- rupt enable/disable. interrupts are enabled when inte flag is set to 1 with the ei instruction and disabled when inte flag is cleared to 0 with the di instruction. when any interrupt occurs, the inte flag is automatically cleared to 0, so that other interrupts are disabled until the ei instruction is executed. (2) interrupt enable bit use an interrupt enable bit of interrupt control registers v1 and v2 to select the corresponding interrupt or skip instruction. table 4 shows the interrupt request flag, interrupt enable bit and skip instruction. table 5 shows the interrupt enable bit function. (3) interrupt request flag when the activated condition for each interrupt is satisfied, the cor- responding interrupt request flag is set to 1. each interrupt request flag is cleared to 0 when either; an interrupt occurs, or the next instruction is skipped with a skip instruction. each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the inte flag or its in- terrupt enable bit. once set, the interrupt request flag retains set until a clear condition is satisfied. accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. if more than one interrupt request flag is set when the interrupt dis- able state is released, the interrupt priority level is as follows shown in table 3. table 3 interrupt sources activated condition level change of int pin timer 1 underflow timer 2 underflow completion of a/d conversion priority level 1 2 3 4 interrupt name external 0 interrupt timer 1 interrupt timer 2 interrupt a/d interrupt table 5 interrupt enable bit function occurrence of interrupt enabled disabled skip instruction invalid valid interrupt enable bit 1 0 interrupt address address 0 in page 1 address 4 in page 1 address 6 in page 1 address c in page 1 table 4 interrupt request flag, interrupt enable bit and skip in- struction function block operations interrupt request flag exf0 t1f t2f adf interrupt name external 0 interrupt timer 1 interrupt timer 2 interrupt a/d interrupt skip instruction snz0 snzt1 snzt2 snzad interrupt enable bit v1 0 v1 2 v1 3 v2 2
1-19 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 (4) internal state during an interrupt the internal state of the microcomputer during an interrupt is as fol- lows (figure 14). program counter (pc) an interrupt address is set in program counter. the address to be executed when returning to the main routine is automatically stored in the stack register (sk). interrupt enable flag (inte) inte flag is cleared to 0 so that interrupts are disabled. interrupt request flag only the request flag for the current interrupt source is cleared to 0. data pointer, carry flag, skip flag, registers a and b the contents of these registers and flags are stored automatically in the interrupt stack register (sdp). (5) interrupt processing when an interrupt occurs, a program at an interrupt address is ex- ecuted after branching a data store sequence to stack register. write the branch instruction to an interrupt service routine at an in- terrupt address. use the rti instruction to return from an interrupt service routine. interrupt enabled by executing the ei instruction is performed after executing 1 instruction (just after the next instruction is executed). accordingly, when the ei instruction is executed just before the rti instruction, interrupts are enabled after returning the main routine. (refer to figure 13) fig. 13 program example of interrupt processing program counter (pc) ............................................................... each interrupt address stack register (sk) .................................................................................................... interrupt enable flag (inte) .................................................................. 0 (interrupt disabled) interrupt request flag (only the flag for the current interrupt source) ................................................................................... 0 data pointer, carry flag, registers a and b, skip flag ........ stored in the interrupt stack register (sdp) automatically the address of main routine to be executed when returning fig. 15 interrupt system diagram fig. 14 internal state when interrupt occurs t1f v1 2 e x f 0 v1 0 address 4 in page 1 address 0 in page 1 t2f v1 3 address 6 in page 1 a d fv 2 2 t i m e r 1 u n d e r f l o w t i m e r 2 u n d e r f l o w c o m p l e t i o n o f a / d c o n v e r s i o n address c in page 1 request flag (state retained) e n a b l e b i t e n a b l e f l a g inte a c t i v a t e d c o n d i t i o n int pin (l e i r t i i n t e r r u p t s e r v i c e r o u t i n e interrupt occurs interrupt is enabled m a i n r o u t i n e : i n t e r r u p t e n a b l e d s t a t e : i n t e r r u p t d i s a b l e d s t a t e function block operations
1-20 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 (6) interrupt control registers interrupt control register v1 interrupt enable bits of external 0, timer 1 and timer 2 are as- signed to register v1. set the contents of this register through register a with the tv1a instruction. the tav1 instruction can be used to transfer the contents of register v1 to register a. interrupt control register v2 the a/d interrupt enable bit is assigned to register v2. set the contents of this register through register a with the tv2a instruc- tion. the tav2 instruction can be used to transfer the contents of register v2 to register a. table 6 interrupt control registers v1 3 v1 2 v1 1 v1 0 v2 3 v2 2 v2 1 v2 0 not used a/d interrupt enable bit not used not used interrupt control register v1 timer 2 interrupt enable bit timer 1 interrupt enable bit not used external 0 interrupt enable bit notes 1: r represents read enabled, and w represents write enabled. 2: these instructions are equivalent to the nop instrucion. interrupt disabled (snzt2 instruction is valid) interrupt enabled (snzt2 instruction is invalid) (note 2) interrupt disabled (snzt1 instruction is valid) interrupt enabled (snzt1 instruction is invalid) (note 2) this bit has no function, but read/write is enabled. interrupt disabled (snz0 instruction is valid) interrupt enabled (snz0 instruction is invalid) (note 2) this bit has no function, but read/write is enabled. interrupt disabled (snzad instruction is valid) interrupt enabled (snzad instruction is invalid) (note 2) this bit has no function, but read/write is enabled. this bit has no function, but read/write is enabled. 0 1 0 1 0 1 0 1 r/w at ram back-up : 0000 2 at reset : 0000 2 r/w at ram back-up : 0000 2 at reset : 0000 2 interrupt control register v2 r/w at ram back-up : 0000 2 at reset : 0000 2 0 1 0 1 0 1 0 1 (7) interrupt sequence interrupts only occur when the respective inte flag, interrupt en- able bits (v1 0 , v1 2 , v1 3 , v2 2 ), and interrupt request flag are 1. the interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied. the interrupt occurs after 3 machine cycles only when the three interrupt conditions are sat- isfied on execution of other than one-cycle instructions (refer to figure 16). function block operations
1-21 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 fig. 16 interrupt sequence t 1 f , t 2 f a d f i n t e x f 0 t 1 t 2 t 3 t 1 t 2 t 3 t 2 t 3 t 1 t 1 t 2 t 3 t 1 t 2 s y s t e m c l o c k t h e p r o g r a m s t a r t s f r o m t h e i n t e r r u p t a d d r e s s . i n t e r r u p t e n a b l e d s t a t e
function block operations 1-22 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 table 7 external interrupt activated conditions name external 0 interrupt input pin int activated condition when the next waveform is input to int pin falling waveform ( h l ) rising waveform ( l h ) both rising and falling waveforms valid waveform selection bit i1 1 i1 2 fig. 17 external interrupt circuit structure external interrupts the 4502 group has the external 0 interrupt. an external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). the external interrupt can be controlled with the interrupt control register i1. 0 1 i 1 2 0 1 e x f 0 i 1 1 snzi0 instruction p 1 3 / i n t k1 3 i 1 3 ( n o t e ) wakeup skip r i s i n g f a l l i n g o n e - s i d e d e d g e d e t e c t i o n c i r c u i t both edges detection circuit e x t e r n a l 0 i n t e r r u p t this symbol represents a parasitic diode on the port. t i m e r 1 c o u n t s t a r t s y n c h r o n i z a t i o n c i r c u i t i n p u t (1) external 0 interrupt request flag (exf0) external 0 interrupt request flag (exf0) is set to 1 when a valid waveform is input to int pin. the valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (refer to figure 16). the state of exf0 flag can be examined with the skip instruction (snz0). use the interrupt control register v1 to select the interrupt or the skip instruction. the exf0 flag is cleared to 0 when an in- terrupt occurs or when the next instruction is skipped with the skip instruction. external 0 interrupt activated condition external 0 interrupt activated condition is satisfied when a valid waveform is input to int pin. the valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. an example of how to use the external 0 interrupt is as follows. ? 1 for the int pin to be in the input enabled state. ? ? 0 with the snz0 instruction. ? ? 1. the external 0 interrupt is now enabled. now when a valid wave- form is input to the int pin, the exf0 flag is set to 1 and the external 0 interrupt occurs.
function block operations 1-23 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 (2) external interrupt control registers interrupt control register i1 register i1 controls the valid waveform for the external 0 inter- rupt. set the contents of this register through register a with the ti1a instruction. the tai1 instruction can be used to transfer the contents of register i1 to register a. table 8 external interrupt control register i1 3 i1 2 i1 1 i1 0 int pin input control bit (note 2) interrupt valid waveform for int pin/ return level selection bit (note 2) int pin edge detection circuit control bit int pin timer 1 control enable bit interrupt control register i1 r/w at ram back-up : state retained at reset : 0000 2 int pin input disabled int pin input enabled falling waveform ( l level of int pin is recognized with the snzi0 instruction)/ l level rising waveform ( h level of int pin is recognized with the snzi0 instruction)/ h level one-sided edge detected both edges detected disabled enabled 0 1 0 1 0 1 0 1 notes 1: r represents read enabled, and w represents write enabled. 2: when the contents of i1 2 and i1 3 are changed, the external interrupt request flag exf0 may be set. accordingly, clear exf0 flag with the snz0 in- struction when the bit 0 (v1 0 ) of register v1 to 0 . in this time, set the nop instruction after the snz0 instruction, for the case when a skip is performed with the snz0 instruction.
function block operations 1-24 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 (3) notes on interrupts ? depending on the input state of the p1 3 /int pin, the external 0 in- terrupt request flag (exf0) may be set when the bit 3 of register i1 is changed. in order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register v1 to 0 (refer to figure 18 ? 0 after executing at least one instruction (refer to figure 18 ? ? ??? ? ??? ? ? ? fig. 18 external 0 interrupt program example-1 ? 0 , the ram back-up mode is selected and the input of int pin is disabled, be careful about the following notes. when the key-on wakeup function of port p1 3 is not used (regis- ter k1 3 = 0 ), clear bits 2 and 3 of register i1 before system enters to the ram back-up mode. (refer to figure 19 ? la 0 ; (00 ?? ? ? fig. 19 external 0 interrupt program example-2 ? depending on the input state of the p1 3 /int pin, the external 0 in- terrupt request flag (exf0) may be set when the bit 2 of register i1 is changed. in order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register v1 to 0 (refer to figure 20 ? 0 after executing at least one instruction (refer to figure 20 ? ? ??? ? ? ?? ? ? ? fig. 20 external 0 interrupt program example-3
function block operations 1-25 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 timers the 4502 group has the following timers. programmable timer the programmable timer has a reload register and enables the frequency dividing ratio to be set. it is decremented from a set- ting value n. when it underflows (count to n + 1), a timer interrupt request flag is set to 1, new data is loaded from the reload reg- ister, and count continues (auto-reload function). fixed dividing frequency timer the fixed dividing frequency timer has the fixed frequency divid- ing ratio (n). an interrupt request flag is set to 1 after every n count of a count pulse. fig. 21 auto-reload function ff 16 n 00 16 n : c o u n t e r i n i t i a l v a l u e c o u n t s t a r t s r e l o a d reload 1st underflow 2nd underflow n+1 coun t n+1 coun t t i m e a n i n t e r r u p t o c c u r s o r a s k i p i n s t r u c t i o n i s e x e c u t e d . t i m e r i n t e r r u p t r e q u e s t f l a g t h e c o n t e n t s o f c o u n t e r 1 0 count source instruction clock prescaler output (orclk) timer 1 underflow prescaler output (orclk) cntr input system clock instruction clock structure frequency divider 8-bit programmable binary down counter (link to int input) 8-bit programmable binary down counter 16-bit fixed dividing frequency binary down counter circuit prescaler timer 1 timer 2 16-bit timer use of output signal timer 1 and 2 count sources timer 2 count source cntr output timer 1 interrupt cntr output timer 2 interrupt watchdog timer (the 16th bit is counted twice) frequency dividing ratio 4, 16 1 to 256 1 to 256 65536 control register w1 w1 w2 w6 w2 w6 the 4502 group timer consists of the following circuits. prescaler : frequency divider timer 1 : 8-bit programmable timer timer 2 : 8-bit programmable timer (timers 1 and 2 have the interrupt function, respectively) 16-bit timer prescaler and timers 1 and 2 can be controlled with the timer con- trol registers w1, w2 and w6. the 16-bit timer is a free counter which is not controlled with the control register. each function is described below. table 9 function related timers
function block operations 1-26 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 fig. 22 timers structure 1 6 - b i t t i m e r ( w d t ) 11 6 i n s t r u c t i o n c l o c k q s q t d w d f 2 orclk x i n 1 / 4 1 / 1 6 w 1 3 0 1 0 1 w 1 2 d i v i s i o n c i r c u i t d i v i d e d b y 8 d i v i d e d b y 4 d i v i d e d b y 2 p 1 2 / c n t r p1 2 output 0 1 w6 0 0 1 w2 3 (tr1ab) t 1 f t2f (tab1) 0 1 w 1 1 w 2 1 , w 2 0 1 1 1 0 0 1 0 0 1 / 2 0 1 w6 1 1 / 2 (t2ab) (tab2) (tab1) (tab2) ( n o t e 2 ) ( n o t e 2 ) t1ab t1ab mr 3 , mr 2 0 0 0 1 1 0 1 1 w 1 0 0 1 q r s 0 1 i 1 2 0 1 i1 1 p 1 3 / i n t ( n o t e 1 ) i 1 0 w 2 2 t i m e r 1 u n d e r f l o w s i g n a l i1 3 r q r s w e f reset signal (note 5) d w d t i n s t r u c t i o n + w r s t i n s t r u c t i o n ( n o t e 4 ) r w d f 1 wrst instruction (note 3) t i m e r 1 ( 8 ) t i m e r 1 i n t e r r u p t r e l o a d r e g i s t e r r 1 ( 8 ) register b r e g i s t e r a timer 2 (8) reload register r2 (8) register b register a t i m e r 2 i n t e r r u p t d a t a i s s e t a u t o m a t i c a l l y f r o m e a c h r e l o a d r e g i s t e r w h e n t i m e r 1 o r 2 u n d e r f l o w s ( a u t o - r e l o a d f u n c t i o n ) n o t e s 1 : t i m e r 1 c o u n t s t a r t s y n c h r o n o u s c i r c u i t i s s e t b y t h e v a l i d e d g e o f p 1 3 / i n t p i n s e l e c t e d b y b i t s 1 ( i 1 1 ) a n d 2 ( i 1 2 ) o f r e g i s t e r i 1 . 2 : c o u n t s o u r c e i s s t o p p e d b y c l e a r i n g t o 0 . 3 : w h e n t h e w r s t i n s t r u c t i o n i s e x e c u t e d a t w d f 1 f l a g = 1 , w d f 1 f l a g i s c l e a r e d t o 0 a n d t h e n e x t i n s t r u c t i o n i s s k i p p e d . w h e n t h e w r s t i n s t r u c t i o n i s e x e c u t e d a t w d f 1 f l a g = 0 , s k i p i s n o t e x e c u t e d . 4 : w h e n t h e d w d t a n d w r s t i n s t r u c t i o n s a r e e x e c u t e d c o n t i n u o u s l y , w e f f l a g i s c l e a r e d t o 0 a n d r e s e t b y w a t c h d o g t i m e r i s n o t e x e c u t e d . 5 : t h e w e f f l a g i s s e t t o 1 a t s y s t e m r e s e t o r r a m b a c k - u p m o d e . instruction clock i n t e r n a l c l o c k g e n e r a t i n g c i r c u i t ( d i v i d e d b y 3 ) p r e s c a l e r one-sided edge detection circuit b o t h e d g e s d e t e c t i o n c i r c u i t falling rising c l o c k g e n e r a t i o n c i r c u i t s y s t e m c l o c k timer 1 underflow signal timer 2 underflow signal r e s e t s i g n a l w a t c h d o g r e s e t s i g n a l
function block operations 1-27 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 table 10 timer control registers 0 1 0 1 0 1 0 1 w2 1 0 0 1 1 stop (state initialized) operating instruction clock divided by 4 instruction clock divided by 16 stop (state retained) operating count start synchronous circuit not selected count start synchronous circuit selected prescaler control bit prescaler dividing ratio selection bit timer 1 control bit timer 1 count start synchronous circuit control bit stop (state retained) operating count auto-stop circuit not selected count auto-stop circuit selected count source timer 1 underflow signal prescaler output (orclk) cntr input system clock timer 2 control bit timer 1 count auto-stop circuit selection bit (note 2) timer 2 count source selection bits 0 1 0 1 w2 0 0 1 0 1 w1 3 w1 2 w1 1 w1 0 w2 3 w2 2 w2 1 w2 0 timer control register w1 r/w at ram back-up : 0000 2 at reset : 0000 2 r/w at ram back-up : 0000 2 at reset : 0000 2 timer control register w2 r/w at ram back-up : state retained at reset : 0000 2 this bit has no function, but read/write is enabled. this bit has no function, but read/write is enabled. timer 1 underflow signal divided by 2 output timer 2 underflow signal divided by 2 output p1 2 (i/o)/cntr input (note 3) p1 2 (input)/cntr input/output (note 3) not used not used cntr output selection bit p1 2 /cntr function selection bit 0 1 0 1 0 1 0 1 timer control register w6 r/w at ram back-up : state retained at reset : 0000 2 notes 1: r represents read enabled, and w represents write enabled. 2: this function is valid only when the timer 1 count start synchronization circuit is selected. 3: cntr input is valid only when cntr input is selected as the timer 2 count source. (1) timer control registers timer control register w1 register w1 controls the count operation of timer 1, the selection of count start synchronous circuit, and the frequency dividing ra- tio and count operation of prescaler. set the contents of this register through register a with the tw1a instruction. the taw1 instruction can be used to transfer the contents of register w1 to register a. timer control register w2 register w2 controls the selection of timer 1 count auto-stop cir- cuit, and the count operation and count source of timer 2. set the contents of this register through register a with the tw2a instruc- tion. the taw2 instruction can be used to transfer the contents of register w2 to register a. timer control register w6 register w6 controls the p1 2 /cntr pin function and the selec- tion of cntr output. set the contents of this register through register a with the tw6a instruction. the taw6 instruction can be used to transfer the contents of register w6 to register a.. (2) prescaler prescaler is a frequency divider. its frequency dividing ratio can be selected. the count source of prescaler is the instruction clock. use the bit 2 of register w1 to select the prescaler dividing ratio and the bit 3 to start and stop its operation. prescaler is initialized, and the output signal (orclk) stops when the bit 3 of register w1 is cleared to 0. w6 3 w6 2 w6 1 w6 0
function block operations 1-28 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 (5) timer interrupt request flags (t1f, t2f) each timer interrupt request flag is set to 1 when each timer underflows. the state of these flags can be examined with the skip instructions (snzt1, snzt2). use the interrupt control register v1 to select an interrupt or a skip instruction. an interrupt request flag is cleared to 0 when an interrupt occurs or when the next instruction is skipped with a skip instruction. (6) count start synchronization circuit (timer 1) timer 1 has the count start synchronous circuit which synchronizes the input of int pin, and can start the timer count operation. timer 1 count start synchronous circuit function is selected by set- ting the bit 0 of register w1 to 1. the control by int pin input can be performed by setting the bit 0 of register i1 to 1. the count start synchronous circuit is set by level change ( h l or l h ) of int pin input. this valid waveform is selected by bits 1 (i1 1 ) and 2 (i1 2 ) of register i1 as follows; i1 1 = 0 : synchronized with one-sided edge (falling or rising) i1 1 = 1 : synchronized with both edges (both falling and rising) when register i1 1 = 0 (synchronized with the one-sided edge), the ris- ing or falling waveform can be selected by the bit 2 of register i1; i1 2 = 0 : falling waveform i1 2 = 1 : rising waveform when timer 1 count start synchronous circuit is used, the count start synchronous circuit is set, the count source is input to each timer by inputting valid waveform to int pin. once set, the count start synchronous circuit is cleared by clearing the bit i1 0 to 0 or reset. however, when the count auto-stop circuit is selected (register w2 2 = 1 ), the count start synchronous circuit is cleared (auto-stop) at the timer 1 underflow. (7) count auto-stop circuit (timer 1) timer 1 has the count auto-stop circuit which is used to stop timer 1 automatically by the timer 1 underflow when the count start syn- chronous circuit is used. the count auto-stop cicuit is valid by setting the bit 2 of register w2 to 1 . it is cleared by the timer 1 underflow and the count source to timer 1 is stopped. this function is valid only when the timer 1 count start synchronous circuit is selected. (3) timer 1 (interrupt function) timer 1 is an 8-bit binary down counter with the timer 1 reload reg- ister (r1). data can be set simultaneously in timer 1 and the reload register (r1) with the t1ab instruction. stop counting and then ex- ecute the t1ab instruction to set data to timer 1. data can be written to reload register (r1) with the tr1ab instruction. when writing data to reload register r1 with the tr1ab instruction, the downcount after the underflow is started from the setting value of reload register r1. timer 1 starts counting after the following process; ? ? 1. however, int pin input can be used as the start trigger for timer 1 count operation by setting the bit 0 of register w1 to 1. also, in this time, the auto-stop function by timer 1 underflow can be performed by setting the bit 2 of register w2 to 1. when a value set is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes 0 ), the timer 1 interrupt request flag (t1f) is set to 1, new data is loaded from reload register r1, and count continues (auto-reload function). data can be read from timer 1 with the tab1 instruction. when reading the data, stop the counter and then execute the tab1 in- struction. (4) timer 2 (interrupt function) timer 2 is an 8-bit binary down counter with the timer 2 reload reg- ister (r2). data can be set simultaneously in timer 2 and the reload register (r2) with the t2ab instruction. stop counting and then ex- ecute the t2ab instruction to set data to timer 2. timer 2 starts counting after the following process; ? ? ? 1. when a value set is n, timer 2 divides the count source signal by n + 1 (n = 0 to 255). once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes 0 ), the timer 2 interrupt request flag (t2f) is set to 1, new data is loaded from reload register r2, and count continues (auto-reload function). data can be read from timer 2 with the tab2 instruction. when reading the data, stop the counter and then execute the tab2 in- struction.
function block operations 1-29 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 (8) timer input/output pin (p1 2 /cntr pin) cntr pin is used to input the timer 2 count source and output the timer 1 and timer 2 underflow signal divided by 2. the p1 2 /cntr pin function can be selected by bit 0 of register w6. the cntr output signal can be selected by bit 1 of register w6. when the cntr input is selected for timer 2 count source, timer 2 counts the falling waveform of cntr input. fig. 23 count timing diagram at cntr input 03 16 02 16 01 16 00 16 ff 16 fe 16 cntr input timer 2 count timer 2 interrupt request flag (t2f) (note) note: this is an example when ff 16 is set to timer 2 reload register r2 l. (9) precautions note the following for the use of timers. prescaler stop the prescaler operation to change its frequency dividing ra- tio. count source stop timer 1 or 2 counting to change its count source. reading the count value stop timer 1 or 2 counting and then execute the tab1 or tab2 instruction to read its data. writing to the timer stop timer 1 or 2 counting and then execute the t1ab or t2ab instruction to write its data. writing to reload register r1 when writing data to reload register r1 while timer 1 is operat- ing, avoid a timing when timer 1 underflows. timer 1 and timer 2 count start timing and count time when op- eration starts count starts from the first rising edge of the count source (2) af- ter timer 1 and timer 2 operations start (1). time to first underflow (3) is shorter (for up to 1 period of the count source) than time among next underflow (4) by the timing to start the timer and count source operations after count starts. when selecting cntr input as the count source of timer 2, timer 2 operates synchronizing with the falling edge of cntr input. fig. 24 t imer count start timing and count time when opera- tion starts (t1, t2) (1) timer count source timer value timer underflow signal 321 032 103 2 count source (cntr input) (2) (3) (4)
function block operations 1-30 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 watchdog timer watchdog timer provides a method to reset the system when a pro- gram run-away occurs. watchdog timer consists of timer wdt(16-bit binary counter), watchdog timer enable flag (wef), and watchdog timer flags (wdf1, wdf2). the timer wdt downcounts the instruction clocks as the count source from ffff 16 after system is released from reset. after the count is started, when the timer wdt underflow occurs (after the count value of timer wdt reaches ffff 16 , the next count pulse is input), the wdf1 flag is set to 1. if the wrst instruction is never executed until the timer wdt un- derflow occurs (until timer wdt counts 65534), wdf2 flag is set to 1, and the reset pin outputs l level to reset the microcom- puter. execute the wrst instruction at each period of 65534 machine cycle or less by software when using watchdog timer to keep the microcomputer operating normally. when the wef flag is set to 1 after system is released from reset, the watchdog timer function is valid. when the dwdt instruction and the wrst instruction are ex- ecuted continuously, the wef flag is cleared to 0 and the watchdog timer function is invalid. the wef flag is set to "1" at system reset or ram back-up mode. the wrst instruction has the skip function. when the wrst in- struction is executed while the wdf1 flag is 1 , the wdf1 flag is cleared to 0 and the next instruction is skipped. when the wrst instruction is executed while the wdf1 flag is 0 , the next instruction is not skipped. the skip function of the wrst instruction can be used even when the watchdog timer function is invalid. fig. 25 watchdog timer function 65534 count (note) value of 16-bit timer (wdt) wdf1 flag ? ? ? ? ? 1. ? 0, the next instruction is skipped. ? 1, wdf2 flag is set to 1 and the watchdog reset signal is output. ? on by the watchdog reset signal and system reset is executed. note: the number of count is equal to the number of machine cycle because the count source of watchdog timer is the instruction clock. ffff 16 0000 16 ? ? ?
function block operations 1-31 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 fig. 26 program example to start/stop watchdog timer fig. 27 program example to enter the ram back-up mode when using the watchdog timer wrst ; wdf1 flag cleared nop di ; interrupt disabled epof ; pof instruction enabled pof when the watchdog timer is used, clear the wdf1 flag at the pe- riod of 65534 machine cycles or less with the wrst instruction. when the watchdog timer is not used, execute the dwdt instruc- tion and the wrst instruction continuously (refer to figure 26). the watchdog timer is not stopped with only the dwdt instruction. the contents of wdf1 flag and timer wdt are initialized at the ram back-up mode. when using the watchdog timer and the ram back-up mode, ini- tialize the wdf1 flag with the wrst instruction just before the microcomputer enters the ram back-up state (refer to figure 27) the watchdog timer function is valid after system is returned from the ram back-up. when not using the watchdog timer function, ex- ecute the dwdt instruction and the wrst instruction continuously every system is returned from the ram back-up, and stop the watchdog timer function. wrst ; wdf1 flag cleared di dwdt ; wat chdog timer function enabled/disabled wrst ; wef and wdf1 flags cleared
function block operations 1-32 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 a/d converter the 4502 group has a built-in a/d conversion circuit that performs conversion by 10-bit successive comparison method. table 11 shows the characteristics of this a/d converter. this a/d converter can also be used as an 8-bit comparator to compare analog volt- ages input from the analog input pin with preset values. table 11 a/d converter characteristics characteristics successive comparison method 10 bits linearity error: 2lsb differential non-linearity error: 0.9lsb 46.5 fig. 28 a/d conversion circuit structure v s s v d d dac da converter tabad 1/6 q 1 3 q 1 1 q1 0 q 1 2 tadab 0 1 4 4 4 4 8 8 8 01 1 8 10 q 1 3 q 1 3 0 1 q1 3 8 ( n o t e 1 ) 8 2 tala q1 3 taq1 t q 1 a adf (1) p 2 0 / a i n 0 2 1 0 10 p 2 1 / a i n 1 p 3 0 / a i n 2 p 3 1 / a i n 3 i a p 3 ( p 3 0 , p 3 1 ) o p 3 a ( p 3 0 , p 3 1 ) i a p 2 ( p 2 0 , p 2 1 ) o p 2 a ( p 2 0 , p 2 1 ) register a (4) register b (4) d a c o p e r a t i o n s i g n a l c o m p a r a t o r 4 - c h a n n el m u l t i - p l e x e d an a l o g s w i t c h i n s t r u c t i o n c l o c k a/d control circuit s u c c e s s i v e c o m p a r i s o n r e g i s t e r ( a d ) ( 1 0 ) a / d i n t e r r u p t c o m p a r a t o r r e g i s t e r ( 8 ) n o t e s 1 : t h i s s w i t c h i s t u r n e d o n o n l y w h e n a / d c o n v e r t e r i s o p e r a t i n g a n d g e n e r a t e s t h e c o m p a r i s o n v o l t a g e . 2 : w r i t i n g / r e a d i n g d a t a t o t h e c o m p a r a t o r r e g i s t e r i s p o s s i b l e o n l y i n t h e c o m p a r a t o r m o d e ( q 1 3 = 1 ) . t h e v a l u e o f t h e c o m p a r a t o r r e g i s t e r i s r e t a i n e d e v e n w h e n t h e m o d e i s s w i t c h e d t o t h e a / d c o n v e r s i o n m o d e ( q 1 3 = 0 ) b e c a u s e i t i s s e p a r a t e d f r o m t h e s u c c e s s i v e c o m p a r i s o n r e g i s t e r ( a d ) . a l s o , t h e r e s o l u t i o n i n t h e c o m p a r a t o r m o d e i s 8 b i t s b e c a u s e t h e c o m p a r a t o r r e g i s t e r c o n s i s t s o f 8 b i t s . ( n o t e 2 )
function block operations 1-33 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 q1 3 q1 2 a/d control register q1 a/d operation mode selection bit not used analog input pin selection bits at reset : 0000 2 at ram back-up : state retained 0 1 0 1 q1 1 0 0 1 1 a/d conversion mode comparator mode this bit has no function, but read/write is enabled. selected pins a in0 a in1 a in2 a in3 note: r represents read enabled, and w represents write enabled. q1 0 0 1 0 1 (1) operating at a/d conversion mode the a/d conversion mode is set by setting the bit 3 of register q1 to 0. (2) successive comparison register ad register ad stores the a/d conversion result of an analog input in 10-bit digital data format. the contents of the high-order 8 bits of this register can be stored in register b and register a with the tabad instruction. the contents of the low-order 2 bits of this reg- ister can be stored into the high-order 2 bits of register a with the tala instruction. however, do not execute these instructions dur- ing a/d conversion. when the contents of register ad is n, the logic value of the com- parison voltage v ref generated from the built-in da converter can be obtained with the reference voltage v dd by the following for- mula: logic value of comparison voltage v ref v ref = ? table 12 a/d control registers (3) a/d conversion completion flag (adf) a/d conversion completion flag (adf) is set to 1 when a/d con- version completes. the state of adf flag can be examined with the skip instruction (snzad). use the interrupt control register v2 to select the interrupt or the skip instruction. the adf flag is cleared to 0 when the interrupt occurs or when the next instruction is skipped with the skip instruction. (4) a/d conversion start instruction (adst) a/d conversion starts when the adst instruction is executed. the conversion result is automatically stored in the register ad. (5) a/d control register q1 register q1 is used to select the operation mode and one of ana- log input pins. q1 1 q1 0 (6) operation description a/d conversion is started with the a/d conversion start instruction (adst). the internal operation during a/d conversion is as follows: ? 000 16 . ? 1, and the comparison voltage v ref is compared with the analog input volt- age v in . ? 1. when the comparison result is v ref > v in , it is cleared to 0. the 4502 group repeats this operation to the lowermost bit of the register ad to convert an analog value to a digital value. a/d con- version stops after 62 machine cycles (46.5 1 as soon as a/d conversion completes (figure 29).
function block operations 1-34 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 table 13 change of successive comparison register ad during a/d conversion comparison voltage (v ref ) value change of successive comparison register ad at starting conversion ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ------------- ------------- ------------- ------------- ------------- ------------- ------------- ------------- fig. 30 setting registers a/d control register q1 a in1 pin selected a/d conversion mode 0001 (bit 3) (bit 0) (7) a/d conversion timing chart figure 29 shows the a/d conversion timing chart. fig. 29 a/d conversion timing chart (8) how to use a/d conversion how to use a/d conversion is explained using as example in which the analog input from p2 1 /a in1 pin is a/d converted, and the high- order 4 bits of the converted data are stored in address m(z, x, y) = (0, 0, 0), the middle-order 4 bits in address m(z, x, y) = (0, 0, 1), and the low-order 2 bits in address m(z, x, y) = (0, 0, 2) of ram. the a/d interrupt is not used in this example. ? ? ? ? ? ? ? ?
function block operations 1-35 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 (9) operation at comparator mode the a/d converter is set to comparator mode by setting bit 3 of the register q1 to 1. below, the operation at comparator mode is described. (10) comparator register in comparator mode, the built-in da comparator is connected to the 8-bit comparator register as a register for setting comparison volt- ages. the contents of register b is stored in the high-order 4 bits of the comparator register and the contents of register a is stored in the low-order 4 bits of the comparator register with the tadab in- struction. when changing from a/d conversion mode to comparator mode, the result of a/d conversion (register ad) is undefined. however, because the comparator register is separated from regis- ter ad, the value is retained even when changing from comparator mode to a/d conversion mode. note that the comparator register can be written and read at only comparator mode. if the value in the comparator register is n, the logic value of com- parison voltage v ref generated by the built-in da converter can be determined from the following formula: (11) comparison result store flag (adf) in comparator mode, the adf flag, which shows completion of a/d conversion, stores the results of comparing the analog input volt- age with the comparison voltage. when the analog input voltage is lower than the comparison voltage, the adf flag is set to 1. the state of adf flag can be examined with the skip instruction (snzad). use the interrupt control register v2 to select the inter- rupt or the skip instruction. the adf flag is cleared to 0 when the interrupt occurs or when the next instruction is skipped with the skip instruction. (12) comparator operation start instruction (adst instruction) in comparator mode, executing adst starts the comparator oper- ating. the comparator stops 8 machine cycles after it has started (6 1. (13) notes for the use of a/d conversion 1 note the following when using the analog input pins also for ports p2 and p3 functions: selection of analog input pins even when p2 0 /a in0 , p2 1 /a in1 , p3 0 /a in2 , p3 1 /a in3 are set to pins for analog input, they continue to function as ports p2 and p3 in- put/output. accordingly, when any of them are used as i/o port and others are used as analog input pins, make sure to set the outputs of pins that are set for analog input to 1. also, the port input function of the pin functions as an analog input is unde- fined. tala instruction when the tala instruction is executed, the low-order 2 bits of register ad is transferred to the high-order 2 bits of register a, si- multaneously, the low-order 2 bits of register a is 0. (14) notes for the use of a/d conversion 2 do not change the operating mode (both a/d conversion mode and comparator mode) of a/d converter with the bit 3 of register q1 while the a/d converter is operating. when the operating mode of a/d converter is changed from the comparator mode to a/d conversion mode with the bit 3 of register q1, note the following; clear the bit 2 of register v2 to 0 to change the operating mode of the a/d converter from the comparator mode to a/d conver- sion mode with the bit 3 of register q1. the a/d conversion completion flag (adf) may be set when the operating mode of the a/d converter is changed from the com- parator mode to the a/d conversion mode. accordingly, set a value to the bit 3 of register q1, and execute the snzad instruc- tion to clear the adf flag. logic value of comparison voltage v ref v ref = ? fig. 31 comparator operation timing chart v dd 256 adst instruction c o m p a r i s o n r e s u l t s t o r e f l a g ( a d f ) 8 m a c h i n e c y c l e s d a c o p e r a t i o n s i g n a l c o m p a r a t o r o p e r a t i o n c o m p l e t e d . ( t h e v a l u e o f a d f i s d e t e r m i n e d )
function block operations 1-36 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 (15) definition of a/d converter accuracy the a/d conversion accuracy is defined below (refer to figure 32). relative accuracy ? 0 to 1. ? 1023 to 1022. ? ? absolute accuracy this means a deviation from the ideal characteristics between 0 to v dd of actual a/d conversion characteristics. fig. 32 definition of a/d conversion accuracy v fst v 0t 1022 v dd 1024 vn: analog input voltage when the output data changes from n to n+1 (n = 0 to 1022) 1lsb at relative accuracy 1lsb at absolute accuracy a a [ l s b ] a c t u a l a / d c o n v e r s i o n c h a r a c t e r i s t i c s a: 1lsb by relative accuracy b: v n+1 v n c: difference between ideal v n and actual v n zero transition voltage (v 0t ) a n a l o g v o l t a g e full-scale transition voltage (v fst ) ideal line of a/d conversion between v 0 v 1022
function block operations 1-37 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 reset function system reset is performed by applying l level to reset pin for 1 machine cycle or more when the following condition is satisfied; the value of supply voltage is the minimum value or more of the recommended operating conditions. then when h level is applied to reset pin, software starts from address 0 in page 0. fig. 33 reset release timing fig. 34 reset pin input waveform and reset operation f(x in ) reset p r o g r a m s t a r t s ( a d d r e s s 0 i n p a g e 0 ) on-chip oscillator (internal oscillator) is counted 5359 times. reset 0.3v dd 0 . 8 5 v d d ( note ) n o t e : k e e p t h e v a l u e o f s u p p l y v o l t a g e t o t h e m i n i m u m v a l u e o r m o r e o f t h e r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s . reset input 1 machine cycle or more = program starts (address 0 in page 0) on-chip oscillator (internal oscillator) is counted 5359 times.
function block operations 1-38 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 fig. 35 structure of reset pin and its peripherals, and power-on reset operation name d 0 , d 1 , d 4 , d 5 d 2 /c, d 3 /k p0 0 , p0 1 , p0 2 , p0 3 p1 0 , p1 1 , p1 2 /cntr, p1 3 /int p2 0 /a in0 , p2 1 /a in1 p3 0 /a in2 , p3 1 /a in3 notes 1: output latch is set to 1. 2: pull-up transistor is turned off. function d 0 , d 1 , d 4 , d 5 d 2 , d 3 p0 0 p0 3 p1 0 p1 3 p2 0 , p2 1 p3 0 , p3 1 state high-impedance (note 1) high-impedance (notes 1, 2) high-impedance (notes 1, 2) high-impedance (notes 1, 2) high-impedance (notes 1, 2) high-impedance (note 1) (1) power-on reset reset can be automatically performed at power on (power-on re- set) by the built-in power-on reset circuit. when the built-in power-on reset circuit is used, the time for the supply voltage to rise from 0 v to 2.0 v must be set to 100 l level to reset pin until the value of supply voltage reaches the minimum operating voltage. table 14 port state at reset r e s e t p i n wef w a t c h d o g r e s e t s i g n a l ( n o t e 1 ) p u l l - u p t r a n s i s t o r ( n o t e 1 ) p o w e r - o n r e s e t c i r c u i t v o l g a t e d r o p d e t e c t i o n c i r c u i t v d d ( n o t e 3 ) 1 0 0 n o t e s 1 : t h i s s y m b o l r e p r e s e n t s a p a r a s i t i c d i o d e . 2 : a p p l i e d p o t e n t i a l t o r e s e t p i n m u s t b e v d d o r l e s s . 3 : k e e p t h e v a l u e o f s u p p l y v o l t a g e t o t h e m i n i m u m v a l u e o r m o r e o f t h e r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s . power-on reset circuit output
function block operations 1-39 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 program counter (pc) .......................................................................................................... address 0 in page 0 is set to program counter. interrupt enable flag (inte) .................................................................................................. power down flag (p) ........................................................................................................... .. external 0 interrupt request flag (exf0) .............................................................................. interrupt control register v1 ................................................................................................. . interrupt control register v2 ................................................................................................. . interrupt control register i1 ................................................................................................. .. timer 1 interrupt request flag (t1f) ..................................................................................... timer 2 interrupt request flag (t2f) ..................................................................................... watchdog timer flags (wdf1, wdf2) .................................................................................. watchdog timer enable flag (wef) ...................................................................................... timer control register w1 ..................................................................................................... timer control register w2 ..................................................................................................... timer control register w6 ..................................................................................................... clock control register mr ..................................................................................................... key-on wakeup control register k0 ...................................................................................... key-on wakeup control register k1 ...................................................................................... key-on wakeup control register k2 ...................................................................................... pull-up control register pu0 ................................................................................................. pull-up control register pu1 ................................................................................................. pull-up control register pu2 ................................................................................................. a/d conversion completion flag (adf) ................................................................................. a/d control register q1 ....................................................................................................... .. carry flag (cy) ............................................................................................................... ....... register a .................................................................................................................... ......... register b .................................................................................................................... ......... register d .................................................................................................................... ......... register e .................................................................................................................... ......... register x .................................................................................................................... ......... register y .................................................................................................................... ......... register z .................................................................................................................... ......... stack pointer (sp) ............................................................................................................ .... oscillation clock ..................................................................... on-chip oscillator (operating) ceramic resonator circuit ..................................................................................... operating rc oscillation circuit ...................................................................................................... stop ? represents undefined. fig. 36 internal state at reset ?? (2) internal state at reset figure 36 shows internal state at reset (they are the same after sys- tem is released from reset). the contents of timers, registers, flags and ram except shown in figure 36 are undefined, so set the ini- tial value to them. 00000000000000 0 (interrupt disabled) 0 0 0 0 0 0 (interrupt disabled) 0 0 0 0 (interrupt disabled) 0000 0 0 0 1 0 0 0 0 (prescaler and timer 1 stopped) 0 0 0 0 (timer 2 stopped) 0000 1100 0000 0000 0000 0000 0000 0000 0 0000 0 0000 0000 ??? ?????? ??
1-40 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 voltage drop detection circuit the built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value. fig. 37 voltage drop detection circuit fig. 38 voltage drop detection circuit operation waveform example function block operations + v r s t v d d q s r r e s e t s i g n a l r e t u r n i n p u t epof instruction +pof2 instruction (continuous execution) ( note 2 ) voltage drop detection circuit reset signal ( note 1 ) v o l t a g e d r o p d e t e c t i o n c i r c u i t notes 1: in the ram back-up mode by the pof2 instruction, the voltage drop detection circuit stops. 2: when the v dd (supply voltage) is vrst (detection voltage) or less, the voltage drop detection circuit reset signal is output. v dd the microcomputer starts operation after the on-chip oscillator (internal oscillator) is counted 5359 times. note 3 v o l t a g e d r o p d e t e c t i o n c i r c u i t r e s e t s i g n a l r e s e t p i n n o t e s 1 : a f t e r s y s t e m i s r e l e a s e d f r o m r e s e t , t h e o n - c h i p o s c i l l a t o r ( i n t e r n a l o s c i l l a t o r ) i s s e l e c t e d a s t h e o p e r a t i o n c l o c k o f t h e m i c r o c o m p u t e r . 2 : r e f e r t o t h e v o l t a g e d r o p d e t e c t i o n c i r c u i t c h a r a c t e r i s t i c s i n t h e e l e c t r i c a l c h a r a c t e r i s t i c s f o r t h e r a t i n g v a l u e o f v r s t ( d e t e c t i o n v o l t a g e ) . 3 : t h e v r s t ( d e t e c t i o n v o l t a g e ) d o e s n o t i n c l u d e h y s t e r e s i s .
1-41 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 ram back-up mode the 4502 group has the ram back-up mode. when the pof or pof2 instruction is executed continuously after the epof instruction, system enters the ram back-up state. the pof or pof2 instruction is equal to the nop instruction when the epof instruction is not executed before the pof or pof2 in- struction. as oscillation stops retaining ram, the function of reset circuit and states at ram back-up mode, current dissipation can be reduced without losing the contents of ram. in the ram back-up mode by the pof instruction, system enters the ram back-up mode and the voltage drop detection cicuit keeps operating. in the ram back-up mode by the pof2 instruction, all internal periperal functions stop. table 15 shows the function and states retained at ram back-up. figure 39 shows the state transition. (1) identification of the start condition warm start (return from the ram back-up state) or cold start (re- turn from the normal reset state) can be identified by examining the state of the power down flag (p) with the snzp instruction. (2) warm start condition when the external wakeup signal is input after the system enters the ram back-up state by executing the epof instruction and pof or pof2 instruction continuously, the cpu starts executing the program from address 0 in page 0. in this case, the p flag is 1. (3) cold start condition the cpu starts executing the program from address 0 in page 0 when; reset pulse is input to reset pin, or reset by watchdog timer is performed, or voltage drop detection circuit is detected by the voltage drop in this case, the p flag is 0. table 15 functions and states retained at ram back-up function program counter (pc), registers a, b, carry flag (cy), stack pointer (sp) (note 2) contents of ram port level selected oscillation circuit timer control register w1 timer control registers w2, w6 clock control register mr interrupt control registers v1, v2 interrupt control register i1 timer 1 function timer 2 function a/d conversion function voltage drop detection circuit a/d control register q1 pull-up control registers pu0 to pu2 key-on wakeup control registers k0 to k2 external 0 interrupt request flag (exf0) timer 1 interrupt request flag (t1f) timer 2 interrupt request flag (t2f) watchdog timer flags (wdf1) watchdog timer enable flag (wef) 16-bit timer (wdt) a/d conversion completion flag (adf) interrupt enable flag (inte) pof2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? o represents that the function can be retained, and ? repre- sents that the function is initialized. registers and flags other than the above are undefined at ram back-up, and set an initial value after returning. 2: the stack pointer (sp) points the level of the stack register and is initialized to 7 at ram back-up. 3: the state of the timer is undefined. 4: initialize the watchdog timer flag wdf1 with the wrst instruction, and then execute the pof or pof2 instruction. 5: this function is operating in the ram back-up mode. when the voltage drop is detected, system reset occurs. 6: as for the d 2 /c pin, the output latch of port c is set to 1 at the ram back-up. however, the output latch of port d 2 is retained. as for the other ports, their output levels are retained at the ram back-up. ram back-up pof ? ? ? ? ? ? ? ? ? ? ? ? ?
1-42 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 (4) return signal an external wakeup signal is used to return from the ram back-up mode because the oscillation is stopped. table 16 shows the return condition for each return source. (5) control registers key-on wakeup control register k0 register k0 controls the port p0 key-on wakeup function. set the contents of this register through register a with the tk0a instruc- tion. in addition, the tak0 instruction can be used to transfer the contents of register k0 to register a. key-on wakeup control register k1 register k1 controls the port p1 key-on wakeup function. set the contents of this register through register a with the tk1a instruc- tion. in addition, the tak1 instruction can be used to transfer the contents of register k0 to register a. key-on wakeup control register k2 register k2 controls the ports p2, d 2 /c and d 3 /k key-on wakeup function. set the contents of this register through register a with the tk2a instruction. in addition, the tak2 instruction can be used to transfer the contents of register k2 to register a. table 16 return source and return condition remarks the key-on wakeup function can be selected by one port unit. set the port using the key-on wakeup function to h level before going into the ram back-up state. select the return level ( l level or h level) with the bit 2 of register i1 ac- cording to the external state before going into the ram back-up state. return condition return by an external l level in- put. external wakeup signal return source port p0 port p1 (note) port p2 ports d 2 /c, d 3 /k port p1 3 /int (note) pull-up control register pu0 register pu0 controls the on/off of the port p0 pull-up transis- tor. set the contents of this register through register a with the tpu0a instruction. pull-up control register pu1 register pu1 controls the on/off of the port p1 pull-up transis- tor. set the contents of this register through register a with the tpu1a instruction. pull-up control register pu2 register pu2 controls the on/off of the ports p2, d 2 /c and d 3 / k pull-up transistor. set the contents of this register through reg- ister a with the tpu2a instruction. interrupt control register i1 register i1 controls the valid waveform of the external 0 inter- rupt, the input control of int pin and the return input level. set the contents of this register through register a with the ti1a in- struction. in addition, the tai1 instruction can be used to transfer the contents of register i1 to register a. return by an external h level or l level input. the return level can be selected with the bit 2 (i1 2 ) of register i1. when the return level is input, the exf0 flag is not set. note: when the bit 3 (k1 3 ) of register k1 is 0 , the key-on wakeup of the int pin is valid ( h or l level). it is 1 , the key-on wakeup of port p1 3 is valid ( l level). function block operations
1-43 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 fig. 39 state transition fig. 40 set source and clear source of the p flag fig. 41 start condition identified example using the snzp in- struction s r q power down flag p p o f o r p o f 2 i n s t r u c t i o n reset inpu t e p o f i n s t r u c t i o n + p o f o r p o f 2 i n s t r u c t i o n epof instruction + program start p = 1 ? y e s w a r m s t a r t cold start no reset ( s t a b i l i z i n g t i m e a ) b o p e r a t i o n s o u r c e c l o c k : c e r a m i c r e s o n a t o r o n - c h i p o s c i l l a t o r : s t o p r c o s c i l l a t i o n c i r c u i t : s t o p a o p e r a t i o n s o u r c e c l o c k : o n - c h i p o s c i l l a t o r c l o c k c e r a m i c r e s o n a t o r : o p e r a t i n g ( n o t e 2 ) r c o s c i l l a t i o n c i r c u i t : s t o p c operation source clock: rc oscillation on-chip oscillator: stop ceramic resonator: stop c m c k i n s t r u c t i o n e x e c u t i o n ( n o t e 3 ) crck instruction execution ( note 3 ) v o l t a g e d r o p d e t e c t e d k e y - o n w a k e u p ( s t a b i l i z i n g t i m e b ) pof instruction execution d r a m b a c k - u p ( v o l t a g e d r o p d e t e c t i o n c i r c u i t i s o p e r a t i n g . ) operation source clock: stop k e y - o n w a k e u p (stabilizing time c ) p o f i n s t r u c t i o n e x e c u t i o n k e y - o n w a k e u p ( s t a b i l i z i n g t i m e b ) pof2 instruction execution k e y - o n w a k e u p (stabilizing time c ) pof2 instruction execution e r a m b a c k - u p ( a l l f u n c t i o n s o f m i c r o c o m p u t e r s t o p ) operation source clock: stop p o f i n s t r u c t i o n e x e c u t i o n k e y - o n w a k e u p k e y - o n w a k e u p (stabilizing time a ) p o f 2 i n s t r u c t i o n e x e c u t i o n s t a b i l i z i n g t i m e a : m i c r o c o m p u t e r s t a r t s i t s o p e r a t i o n a f t e r c o u n t i n g t h e o n - c h i p o s c i l l a t o r c l o c k 5 3 5 9 t i m e s b y h a r d w a r e . s t a b i l i z i n g t i m e b : m i c r o c o m p u t e r s t a r t s i t s o p e r a t i o n a f t e r c o u n t i n g t h e f ( x i n ) 5 3 5 9 t i m e s b y h a r d w a r e . s t a b i l i z i n g t i m e c : m i c r o c o m p u t e r s t a r t s i t s o p e r a t i o n a f t e r c o u n t i n g t h e f ( x i n ) 1 6 5 t i m e s b y h a r d w a r e . n o t e s 1 : c o n t i n u o u s e x e c u t i o n o f t h e e p o f i n s t r u c t i o n a n d t h e p o f o r p o f 2 i n s t r u c t i o n i s r e q u i r e d t o g o i n t o t h e r a m b a c k - u p s t a t e . 2 : t h r o u g h t h e c e r a m i c r e s o n a t o r i s o p e r a t i n g , t h e o n - c h i p o s c i l l a t o r c l o c k i s s e l e c t e d a s t h e o p e r a t i o n s o u r c e c l o c k . 3 : t h e o s c i l l a t o r c l o c k c o r r e s p o n d i n g t o e a c h i n s t r u c t i o n i s s e l e c t e d a s t h e o p e r a t i o n s o u r c e c l o c k , a n d t h e o n - c h i p o s c i l l a t o r i s s t o p p e d . ( s t a b i l i z i n g t i m e a ) operating o p e r a t i n g o p e r a t i n g function block operations
1-44 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 table 17 key-on wakeup control register k0 3 k0 2 k0 1 k0 0 key-on wakeup control register k0 key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used port p0 3 key-on wakeup control bit port p0 2 key-on wakeup control bit port p0 1 key-on wakeup control bit port p0 0 key-on wakeup control bit at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 r/w note: r represents read enabled, and w represents write enabled. k1 3 k1 2 k1 1 k1 0 key-on wakeup control register k1 p1 3 key-on wakeup not used/int pin key-on wakeup used p1 3 key-on wakeup used/int pin key-on wakeup not used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used port p1 3 /int key-on wakeup control bit port p1 2 /cntr key-on wakeup control bit port p1 1 key-on wakeup control bit port p1 0 key-on wakeup control bit at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 r/w k2 3 k2 2 k2 1 k2 0 key-on wakeup control register k2 key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used port d 3 /k key-on wakeup control bit port d 2 /c key-on wakeup control bit port p2 1 /a in1 key-on wakeup control bit port p2 0 /a in0 key-on wakeup control bit at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 r/w function block operations
1-45 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 pu0 3 pu0 2 pu0 1 pu0 0 pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on port p0 3 pull-up transistor control bit port p0 2 pull-up transistor control bit port p0 1 pull-up transistor control bit port p0 0 pull-up transistor control bit pull-up control register pu0 at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 w table 18 pull-up control register and interrupt control register pu1 3 pu1 2 pu1 1 pu1 0 pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on port p1 3 /int pull-up transistor control bit port p1 2 /cntr pull-up transistor control bit port p1 1 pull-up transistor control bit port p1 0 pull-up transistor control bit pull-up control register pu1 at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 w pu2 3 pu2 2 pu2 1 pu2 0 pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on port d 3 /k pull-up transistor control bit port d 2 /c pull-up transistor control bit port p2 1 /a in1 pull-up transistor control bit port p2 0 /a in0 pull-up transistor control bit pull-up control register pu2 at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 w i1 3 i1 2 i1 1 i1 0 int pin input control bit (note 2) interrupt valid waveform for int pin/ return level selection bit (note 2) int pin edge detection circuit control bit int pin timer 1 control enable bit notes 1: r represents read enabled, and w represents write enabled. 2: when the contents of i1 2 and i1 3 are changed, the external interrupt request flag exf0 may be set. accordingly, clear exf0 flag with the snz0 in- struction when the bit 0 (v1 0 ) of register v1 to 0 . in this time, set the nop instruction after the snz0 instruction, for the case when a skip is performed with the snz0 instruction. interrupt control register i1 r/w at ram back-up : state retained at reset : 0000 2 int pin input disabled int pin input enabled falling waveform ( l level of int pin is recognized with the snzi0 instruction)/ l level rising waveform ( h level of int pin is recognized with the snzi0 instruction)/ h level one-sided edge detected both edges detected disabled enabled 0 1 0 1 0 1 0 1 function block operations
1-46 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 clock control the clock control circuit consists of the following circuits. on-chip oscillator (internal oscillator) ceramic resonator rc oscillation circuit multi-plexer (clock selection circuit) frequency divider internal clock generating circuit fig. 42 clock control circuit structure the system clock and the instruction clock are generated as the source clock for operation by these circuits. figure 42 shows the structure of the clock control circuit. the 4502 group operates by the on-chip oscillator clock (f(ring)) which is the internal oscillator after system is released from reset. also, the ceramic resonator or the rc oscillation can be used for the source oscillation (f(x in )) of the 4502 group. the cmck in- struction or crck instruction is executed to select the ceramic resonator or rc oscillator, respectively. m r 3 , m r 2 0 0 0 1 1 0 1 1 q s qr q s r c r c k i n s t r u c t i o n q s r cmck instruction q s r reset pin x o u t x i n k e y - o n w a k e u p s i g n a l instruction clock c o u n t e r wait time (note 2) control circuit program start signal rc oscillation circuit d i v i s i o n c i r c u i t d i v i d e d b y 8 d i v i d e d b y 4 d i v i d e d b y 2 i n t e r n a l c l o c k g e n e r a t i o n c i r c u i t ( d i v i d e d b y 3 ) notes 1: system operates by the on-chip oscillator clock (f(ring)) until the cmck or crck instruction is executed after system is released from reset. 2: the wait time control circuit is used to generate the time required to stabilize the f(x in ) oscillation. after the certain oscillation stabilizing wait time elapses, the program start signal is output. this circuit operates when system is released from reset or returned from ram back-up. system clock o n - c h i p o s c i l l a t o r ( i n t e r n a l o s c i l l a t o r ) ( n o t e 1 ) multiplexer c e r a m i c r e s o n a t o r c i r c u i t pof or epof instruction + pof2 instruction function block operations
1-47 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 fig. 43 switch to ceramic resonance/rc oscillation fig. 44 handling of x in and x out when operating on-chip oscillator fig. 45 ceramic resonator external circuit fig. 46 external rc oscillation circuit execute the cmck instruc- tion in program. note: externally connect a damping resistor rd depending on the oscillation frequency. (a feedback resistor is built-in.) use the resonator manu- facturer s recommended value because constants such as ca- pacitance depend on the resonator. (1) selection of source oscillation (f(x in )) the ceramic resonator or rc oscillation can be used for the source oscillation of the mcu. after system is released from reset, the mcu starts operation by the clock output from the on-chip oscillator which is the internal os- cillator. when the ceramic resonator is used, execute the cmck instruc- tion. when the rc oscillation is used, execute the crck instruction. the oscillation circuit by the cmck or crck instruction can be selected only at once. the oscillation circuit corresponding to the first executed one of these two instructions is valid. other os- cillation circuit and the on-chip oscillator stop. execute the cmck or the crck instruction in the initial setting rou- tine of program (executing it in address 0 in page 0 is recommended). also, when the cmck or the crck instruction is not executed in program, the mcu operates by the on-chip oscilla- tor. (2) on-chip oscillator operation when the mcu operates by the on-chip oscillator as the source os- cillation (f(x in )) without using the ceramic resonator or the rc oscillator, connect x in pin to v ss and leave x out pin open (figure 44). the clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. be careful that variable frequencies when designing application products. (3) ceramic resonator when the ceramic resonator is used as the source oscillation (f(x in )), connect the ceramic resonator and the external circuit to pins x in and x out at the shortest distance. then, execute the cmck instruction. a feedback resistor is built in between pins x in and x out (figure 45). (4) rc oscillation when the rc oscillation is used as the source oscillation (f(x in )), connect the x in pin to the external circuit of resistor r and the ca- pacitor c at the shortest distance and leave x out pin open. then, execute the crck instruction (figure 46). the frequency is affected by a capacitor, a resistor and a micro- computer. so, set the constants within the range of the frequency limits. * 4 5 0 2 x i n x o u t r c * e x e c u t e t h e c r c k i n s t r u c t i o n i n p r o g r a m . 4 5 0 2 x in x o u t rd c in c out 4 5 0 2 x i n x o u t * d o n o t u s e t h e c m c k i n s t r u c t i o n a n d c r c k i n s t r u c t i o n i n p r o g r a m . reset o n - c h i p o s c i l l a t o r o p e r a t i o n c m c k i n s t r u c t i o n crck instruction ceramic resonator valid on-chip oscillator stop rc oscillation stop r c o s c i l l a t i o n v a l i d o n - c h i p o s c i l l a t o r s t o p c e r a m i c r e s o n a t o r s t o p function block operations
1-48 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 (5) external clock when the external signal clock is used as the source oscillation (f(x in )), connect the x in pin to the clock source and leave x out pin open. then, execute the cmck instruction (figure 47). be careful that the maximum value of the oscillation frequency when using the external clock differs from the value when using the ceramic resonator (refer to the recommended operating condition). also, note that the ram back-up mode (pof and pof2 instruc- tions) cannot be used when using the external clock. (6) clock control register mr register mr controls system clock. set the contents of this register through register a with the tmra instruction. in addition, the tamr instruction can be used to transfer the contents of register mr to register a. table 19 clock control register mr fig. 47 external clock input circuit rom ordering method please submit the information described below when ordering mask rom. (1) mask rom order confirmation form ..................................... 1 (2) data to be written into mask rom ............................... eprom (three sets containing the identical data) (3) mark specification form .......................................................... 1 ? renesas technology corp. homepage (http://www.renesas.com/en/rom). note : r represents read enabled, and w represents write enabled. mr 3 clock control register mr system clock f(x in ) (high-speed mode) f(x in )/2 (middle-speed mode) f(x in )/4 (low-speed mode) f(x in )/8 (default mode) this bit has no function, but read/write is enabled. this bit has no function, but read/write is enabled. at reset : 1100 2 at ram back-up : 1100 2 mr 3 0 0 1 1 r/w not used not used system clock selection bits 0 1 0 1 mr 2 0 1 0 1 mr 1 mr 0 mr 2 4 5 0 2 x i n x o u t e x t e r n a l o s c i l l a t i o n c i r c u i t v d d v ss e x e c u t e t h e c m c k i n s t r u c t i o n i n p r o g r a m . * function block operations
1-49 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 list of precautions ? ? ? ? ? ? ? ? ? ? 2 count source (cntr input) (2) (3) (4) 10 11 12 13 14
1-50 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 list of precautions note [2] on bit 3 of register i1 when the bit 3 of register i1 is cleared to 0 , the ram back-up mode is selected and the input of int pin is disabled, be careful about the following notes. when the key-on wakeup function of port p1 3 is not used (regis- ter k1 3 = 0 ), clear bits 2 and 3 of register i1 before system enters to the ram back-up mode. (refer to figure 50 ? ?? ? ? fig. 50 external 0 interrupt program example-2 la 4 ; ( ??? ? ? ?? ? ? ? fig. 51 external 0 interrupt program example-3 la 4 ; ( ??? ? ??? ? ? ? fig. 49 external 0 interrupt program example-1 p1 3 /int pin note [1] on bit 3 of register i1 when the input of the int pin is controlled with the bit 3 of regis- ter i1 in software, be careful about the following notes. depending on the input state of the p1 3 /int pin, the external 0 in- terrupt request flag (exf0) may be set when the bit 3 of register i1 is changed. in order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register v1 to 0 (refer to figure 49 ? 0 after executing at least one instruction (refer to figure 49 ? ? l level to reset pin until the value of supply voltage reaches the minimum operating voltage. 16 note [3] on bit 2 of register i1 when the interrupt valid waveform of the p1 3 /int pin is changed with the bit 2 of register i1 in software, be careful about the following notes. depending on the input state of the p1 3 /int pin, the external 0 in- terrupt request flag (exf0) may be set when the bit 2 of register i1 is changed. in order to avoid the occurrence of an unexpected in- terrupt, clear the bit 0 of register v1 to 0 (refer to figure 51 ? 0 after executing at least one instruction (refer to figure 51 ? ?
1-51 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 list of precautions fig. 53 analog input external circuit example-1 fig. 54 analog input external circuit example-2 notes for the use of a/d conversion 2 do not change the operating mode (both a/d conversion mode and comparator mode) of a/d converter with the bit 3 of register q1 while the a/d converter is operating. when the operating mode of a/d converter is changed from the comparator mode to a/d conversion mode with the bit 3 of regis- ter q1, note the following; clear the bit 2 of register v2 to 0 (refer to figure 52 ? the a/d conversion completion flag (adf) may be set when the operat- ing mode of the a/d converter is changed from the comparator mode to the a/d conversion mode. accordingly, set a value to the bit 3 of register q1, and execute the snzad instruction to clear the adf flag. fig. 52 a/d conversion interrupt program example sensor a in about 1k ? ? ?? ? ??? ? notes for the use of a/d conversion 1 note the following when using the analog input pins also for ports p2 and p3 functions: selection of analog input pins even when p2 0 /a in0 , p2 1 /a in1 , p3 0 /a in2 , p3 1 /a in3 are set to pins for analog input, they continue to function as ports p2 and p3 input/ output. accordingly, when any of them are used as i/o port and oth- ers are used as analog input pins, make sure to set the outputs of pins that are set for analog input to 1. also, the port input function of the pin functions as an analog input is undefined. tala instruction when the tala instruction is executed, the low-order 2 bits of register ad is transferred to the high-order 2 bits of register a, si- multaneously, the low-order 2 bits of register a is 0. 20 electric characteristic differences between mask rom and one time prom version mcu there are differences in electric characteristics, operation mar- gin, noise immunity, and noise radiation between mask rom and one time prom version mcus due to the difference in the manufacturing processes. when manufacturing an application system with the one time prom version and then switching to use of the mask rom ver- sion, please perform sufficient evaluations for the commercial samples of the mask rom version. 23 22
1-52 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 control registers i1 3 i1 2 i1 1 i1 0 int pin input control bit (note 3) interrupt valid waveform for int pin/ return level selection bit (note 3) int pin edge detection circuit control bit int pin timer 1 control enable bit interrupt control register i1 r/w at ram back-up : state retained at reset : 0000 2 int pin input disabled int pin input enabled falling waveform ( l level of int pin is recognized with the snzi0 instruction)/ l level rising waveform ( h level of int pin is recognized with the snzi0 instruction)/ h level one-sided edge detected both edges detected disabled enabled 0 1 0 1 0 1 0 1 mr 3 clock control register mr system clock f(x in ) (high-speed mode) f(x in )/2 (middle-speed mode) f(x in )/4 (low-speed mode) f(x in )/8 (default mode) this bit has no function, but read/write is enabled. this bit has no function, but read/write is enabled. at reset : 1100 2 at ram back-up : 1100 2 mr 3 0 0 1 1 r/w not used not used system clock selection bits 0 1 0 1 mr 2 0 1 0 1 mr 1 mr 0 mr 2 this bit has no function, but read/write is enabled. interrupt disabled (snzad instruction is valid) interrupt enabled (snzad instruction is invalid) (note 2) this bit has no function, but read/write is enabled. this bit has no function, but read/write is enabled. r/w v1 3 v1 2 v1 1 v1 0 v2 3 v2 2 v2 1 v2 0 not used a/d interrupt enable bit not used not used interrupt control register v2 at ram back-up : 0000 2 at reset : 0000 2 0 1 0 1 0 1 0 1 interrupt control register v1 timer 2 interrupt enable bit timer 1 interrupt enable bit not used external 0 interrupt enable bit interrupt disabled (snzt2 instruction is valid) interrupt enabled (snzt2 instruction is invalid) (note 2) interrupt disabled (snzt1 instruction is valid) interrupt enabled (snzt1 instruction is invalid) (note 2) this bit has no function, but read/write is enabled. interrupt disabled (snz0 instruction is valid) interrupt enabled (snz0 instruction is invalid) (note 2) 0 1 0 1 0 1 0 1 r/w at ram back-up : 0000 2 at reset : 0000 2 r/w at ram back-up : 0000 2 at reset : 0000 2 notes 1: r represents read enabled, and w represents write enabled. 2: these instructions are equivalent to the nop instruction. 3: when the contents of i1 2 and i1 3 are changed, the external interrupt request flag exf0 may be set. accordingly, clear exf0 flag with the snz0 in- struction when the bit 0 (v1 0 ) of register v1 to 0 . in this time, set the nop instruction after the snz0 instruction, for the case when a skip is performed with the snz0 instruction. control registers
1-53 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 0 1 0 1 0 1 0 1 w2 1 0 0 1 1 stop (state initialized) operating instruction clock divided by 4 instruction clock divided by 16 stop (state retained) operating count start synchronous circuit not selected count start synchronous circuit selected prescaler control bit prescaler dividing ratio selection bit timer 1 control bit timer 1 count start synchronous circuit control bit stop (state retained) operating count auto-stop circuit not selected count auto-stop circuit selected count source timer 1 underflow signal prescaler output (orclk) cntr input system clock timer 2 control bit timer 1 count auto-stop circuit selection bit (note 2) timer 2 count source selection bits 0 1 0 1 w2 0 0 1 0 1 w1 3 w1 2 w1 1 w1 0 timer control register w1 r/w at ram back-up : 0000 2 at reset : 0000 2 r/w at ram back-up : 0000 2 at reset : 0000 2 timer control register w2 r/w at ram back-up : state retained at reset : 0000 2 this bit has no function, but read/write is enabled. this bit has no function, but read/write is enabled. timer 1 underflow signal divided by 2 output timer 2 underflow signal divided by 2 output p1 2 (i/o)/cntr input (note 3) p1 2 (input)/cntr input/output (note 3) not used not used cntr output selection bit p1 2 /cntr function selection bit 0 1 0 1 0 1 0 1 timer control register w6 r/w at ram back-up : state retained at reset : 0000 2 notes 1: r represents read enabled, and w represents write enabled. 2: this function is valid only when the timer 1 count start synchronization circuit is selected. 3: cntr input is valid only when cntr input is selected as the timer 2 count source. q1 3 q1 2 a/d control register q1 a/d operation mode selection bit not used analog input pin selection bits at reset : 0000 2 at ram back-up : state retained 0 1 0 1 q1 1 0 0 1 1 a/d conversion mode comparator mode this bit has no function, but read/write is enabled. selected pins a in0 a in1 a in2 a in3 q1 0 0 1 0 1 r/w q1 1 q1 0 w2 3 w2 2 w2 1 w2 0 w6 3 w6 2 w6 1 w6 0 control registers
1-54 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 k0 3 k0 2 k0 1 k0 0 key-on wakeup control register k0 key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used port p0 3 key-on wakeup control bit port p0 2 key-on wakeup control bit port p0 1 key-on wakeup control bit port p0 0 key-on wakeup control bit at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 r/w note: r represents read enabled, and w represents write enabled. k1 3 k1 2 k1 1 k1 0 key-on wakeup control register k1 p1 3 key-on wakeup not used/int pin key-on wakeup used p1 3 key-on wakeup used/int pin key-on wakeup not used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used port p1 3 /int key-on wakeup control bit port p1 2 /cntr key-on wakeup control bit port p1 1 key-on wakeup control bit port p1 0 key-on wakeup control bit at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 r/w k2 3 k2 2 k2 1 k2 0 key-on wakeup control register k2 key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used port d 3 /k key-on wakeup control bit port d 2 /c key-on wakeup control bit port p2 1 /a in1 key-on wakeup control bit port p2 0 /a in0 key-on wakeup control bit at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 r/w control registers
1-55 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 pu0 3 pu0 2 pu0 1 pu0 0 pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on port p0 3 pull-up transistor control bit port p0 2 pull-up transistor control bit port p0 1 pull-up transistor control bit port p0 0 pull-up transistor control bit pull-up control register pu0 at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 w pu1 3 pu1 2 pu1 1 pu1 0 pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on port p1 3 /int pull-up transistor control bit port p1 2 /cntr pull-up transistor control bit port p1 1 pull-up transistor control bit port p1 0 pull-up transistor control bit pull-up control register pu1 at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 w pu2 3 pu2 2 pu2 1 pu2 0 pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on port d 3 /k pull-up transistor control bit port d 2 /c pull-up transistor control bit port p2 1 /a in1 pull-up transistor control bit port p2 0 /a in0 pull-up transistor control bit pull-up control register pu2 at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 w notes 1: r represents read enabled, and w represents write enabled. control registers
instructions 1-56 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 symbol a b dr e q1 v1 v2 i1 w1 w2 w6 mr k0 k1 k2 pu0 pu1 pu2 x y z dp pc pc h pc l sk sp cy r1 r2 t1 t2 t1f t2f contents register a (4 bits) register b (4 bits) register d (3 bits) register e (8 bits) a/d control register q1 (4 bits) interrupt control register v1 (4 bits) interrupt control register v2 (4 bits) interrupt control register i1 (4 bits) timer control register w1 (4 bits) timer control register w2 (4 bits) timer control register w6 (4 bits) clock control register mr (4 bits) key-on wakeup control register k0 (4 bits) key-on wakeup control register k1 (4 bits) key-on wakeup control register k2 (4 bits) pull-up control register pu0 (4 bits) pull-up control register pu1 (4 bits) pull-up control register pu2 (4 bits) register x (4 bits) register y (4 bits) register z (2 bits) data pointer (10 bits) (it consists of registers x, y, and z) program counter (14 bits) high-order 7 bits of program counter low-order 7 bits of program counter stack register (14 bits ? ? contents of registers and memories negate, flag unchanged after executing instruction ram address pointed by the data pointer label indicating address a 6 a 5 a 4 a 3 a 2 a 1 a 0 label indicating address a 6 a 5 a 4 a 3 a 2 a 1 a 0 in page p 5 p 4 p 3 p 2 p 1 p 0 hex. c + hex. number x (also same for others) symbol wdf1 wef inte exf0 p adf d p0 p1 p2 p3 c k x y z p n i j a 3 a 2 a 1 a 0 ? m(dp) a p, a c + x note : some instructions of the 4502 group has the skip function to unexecute the next described instruction. the 4502 group jus t invalidates the next instruc- tion when a skip is performed. the contents of program counter is not increased by 2. accordingly, the number of cycles does no t change even if skip is not performed. however, the cycle count becomes 1 if the tabp p, rt, or rts instruction is skipped. instructions the 4502 group has the 113 instructions. each instruction is de- scribed as follows; (1) index list of instruction function (2) machine instructions (index by alphabet) (3) machine instructions (index by function) (4) instruction code table symbol the symbols shown below are used in the following list of instruc- tion function and the machine instructions.
instructions 1-57 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 index list of instruction function group- ing ram addresses mnemonic xami j tma j la n tabp p am amc a n and or sc rc szc cma rar function (a) dr 0 , a 3 a 0 ) (b) 4 (a) 0 (pc) 1 (a) e 4 ) e 0 ) e 4 ) (a) e 0 ) (dr 2 dr 0 ) a 0 ) (a 2 a 0 ) dr 0 ) (a 3 ) a 0 ) sp 0 ) (a 3 ) 1 (a) 1 ram to register transfer arithmetic operation ram to register transfer register to register transfer group- ing page 77, 90 83, 90 82, 90 88, 90 83, 90 78, 90 83, 90 78, 90 83, 90 82, 90 81, 90 67, 90 68, 90 67, 90 64, 90 80, 90 88, 90 88, 90 page 89, 90 85, 90 67, 92 78, 92 61, 92 61, 92 61, 92 62, 92 69, 92 72, 92 71, 92 76, 92 64, 92 70, 92 note: p is 0 to 15 for m34502m2, p is 0 to 31 for m34502m4/e4.
instructions 1-58 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 index list of instruction function (continued) group- ing function (mj(dp)) a 0 (pc h ) a 0 (pc h ) dr 0 , a 3 a 0 ) (sp) a 0 (sp) a 0 (sp) dr 0 , a 3 a 0 ) (pc) 1 (pc) 1 (pc) 1 comparison operation subroutine operation branch operation bit operation return operation mnemonic sb j rb j szb j seam sea n b a bl p, a bla p bm a bml p, a bmla p rti rt rts group- ing page 72, 92 70, 92 75, 92 73, 92 73, 92 62, 94 62, 94 62, 94 63, 94 63, 94 63, 94 72, 94 71, 94 72, 94 function (inte) h ? i1 2 = 0 : (int) = l ? (a) t1 4 ) (a) t1 0 ) (r1 7 r1 4 ) t1 4 ) r1 0 ) t1 0 ) t2 4 ) (a) t2 0 ) (r2 7 r2 4 ) t2 4 ) r2 0 ) t2 0 )
instructions 1-59 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 index list of instruction function (continued) group- ing group- ing function (r1 7 r1 4 ) r1 0 ) a 1 ) ad 6 ) (a) ad 2 ) in comparator mode (q1 3 = 1), (b) ad 4 ) (a) ad 0 ) (a 3 , a 2 ) ad 4 ) ad 0 )
instructions 1-60 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 mnemonic nop pof pof2 epof snzp dwdt wrst cmck crck tamr tmra function (pc) index list of instruction function (continued) group- ing page 68, 100 70, 100 70, 100 65, 100 75, 100 65, 100 88, 100 64, 100 64, 100 80, 100 85, 100
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 instructions 1-61 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 machine instructions (index by alphabet) a n (add n and accumulator) 000110nnnn 06n 11 overflow = 0 grouping: arithmetic operation description: adds the value n in the immediate field to register a, and stores a result in register a. the contents of carry flag cy remains unchanged. skips the next instruction when there is no overflow as the result of operation. executes the next instruction when there is overflow as the result of operation. operation: (a) adst (a/d conversion start) 1010011111 29f 11 grouping: a/d conversion operation description: clears (0) to a/d conversion completion flag adf, and the a/d conversion at the a/d conversion mode (q1 3 = 0) or the compara- tor operation at the comparator mode (q1 3 = 1) is started. operation: (adf) am (add accumulator and memory) 0000001010 00a 11 grouping: arithmetic operation description: adds the contents of m(dp) to register a. stores the result in register a. the contents of carry flag cy remains unchanged. operation: (a) amc (add accumulator, memory and carry) 0000001011 00b 11 0/1 grouping: arithmetic operation description: adds the contents of m(dp) and carry flag cy to register a. stores the result in regis- ter a and carry flag cy. operation: (a)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 instructions 1-62 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 and (logical and between accumulator and memory) 0000011000 018 11 grouping: arithmetic operation description: takes the and operation between the con- tents of register a and the contents of m(dp), and stores the result in register a. operation: (a) b a (branch to address a) 011a 6 a 5 a 4 a 3 a 2 a 1 a 0 1a 11 grouping: branch operation description: branch within a page : branches to address a in the identical page. note: specify the branch address within the page including this instruction. operation: (pc l ) bl p, a (branch long to address a in page p) 00111p 4 p 3 p 2 p 1 p 0 0p 22 grouping: branch operation description: branch out of a page : branches to address a in page p. note: p is 0 to 15 for m34502m2, and p is 0 to 31 for m34502m4/e4. operation: (pc h ) bla p (branch long to address (d) + (a) in page p) 0000010000 010 22 grouping: branch operation description: branch out of a page : branches to address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers d and a in page p. note: p is 0 to 15 for m34502m2, and p is 0 to 31 for m34502m4/e4. 8 +a 2 16 100a 6 a 5 a 4 a 3 a 2 a 1 a 0 2aa e +p operation: (pc h ) dr 0 , a 3 a 0 ) 2 16 100p 4 00p 3 p 2 p 1 p 0 2pp machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 instructions 1-63 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 bm a (branch and mark to address a in page 2) 010a 6 a 5 a 4 a 3 a 2 a 1 a 0 1aa 11 grouping: subroutine call operation description: call the subroutine in page 2 : calls the subroutine at address a in page 2. note: subroutine extending from page 2 to an- other page can also be called with the bm instruction when it starts on page 2. be careful not to over the stack because the maximum level of subroutine nesting is 8. operation: (sp) a 0 bml p, a (branch and mark long to address a in page p) 00110p 4 p 3 p 2 p 1 p 0 0p 22 grouping: subroutine call operation description: call the subroutine : calls the subroutine at address a in page p. note: p is 0 to 15 for m34502m2, and p is 0 to 31 for m34502m4/e4. be careful not to over the stack because the maximum level of subroutine nesting is 8. operation: (sp) a 0 bmla p (branch and mark long to address (d) + (a) in page p) 0000110000 030 22 grouping: subroutine call operation description: call the subroutine : calls the subroutine at address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 speci- fied by registers d and a in page p. note: p is 0 to 15 for m34502m2, and p is 0 to 31 for m34502m4/e4. be careful not to over the stack because the maximum level of subroutine nesting is 8. cld (clear port d) 0000010001 011 11 grouping: input/output operation description: sets (1) to port d. operation: (d) operation: (sp) dr 0 , a 3 a 0 ) 2 16 100p 4 00p 3 p 2 p 1 p 0 2pp machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 instructions 1-64 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 cma (complement of accumulator) 0000011100 01c 11 grouping: arithmetic operation description: stores the one s complement for register a s contents in register a. operation: (a) cmck (clock select: ceramic resonance clock) 1010011010 29a 11 grouping: other operation description: selects the ceramic resonance circuit and stops the on-chip oscillator. operation: ceramic resonance circuit selected crck (clock select: rc oscillation clock) 1010011011 29b 11 grouping: other operation description: selects the rc oscillation circuit and stops the on-chip oscillator. operation: rc oscillation circuit selected dey (decrement register y) 0000010111 017 11 (y) = 15 grouping: ram addresses description: subtracts 1 from the contents of register y. as a result of subtraction, when the con- tents of register y is 15, the next instruction is skipped. when the contents of register y is not 15, the next instruction is executed. operation: (y) 1 machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 instructions 1-65 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 di (disable interrupt) 0000000100 004 11 grouping: interrupt control operation description: clears (0) to interrupt enable flag inte, and disables the interrupt. note: interrupt is disabled by executing the di in- struction after executing 1 machine cycle. operation: (inte) dwdt (disable watchdog timer) 1010011100 29c 11 grouping: other operation description: stops the watchdog timer function by the wrst instruction after executing the dwdt instruction. operation: stop of watchdog timer function enabled epof (enable pof instruction) 0001011011 05b 11 grouping: other operation description: makes the immediate after pof or pof2 instruction valid by executing the epof in- struction. operation: pof instruction, pof2 instruction valid ei (enable interrupt) 0000000101 005 11 grouping: interrupt control operation description: sets (1) to interrupt enable flag inte, and enables the interrupt. note: interrupt is enabled by executing the ei in- struction after executing 1 machine cycle. operation: (inte) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 instructions 1-66 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 iak (input accumulator from port k) 1001101111 26f 11 grouping: input/output operation description: transfers the contents of port k to the bit 0 (a 0 ) of register a. note: after this instruction is executed, 0 is stored to the high-order 3 bits (a 3 a 1 ) of register a. operation: (a 0 ) a 1 ) iap0 (input accumulator from port p0) 1001100000 260 11 grouping: input/output operation description: transfers the input of port p0 to register a. iap1 (input accumulator from port p1) 1001100001 261 11 grouping: input/output operation description: transfers the input of port p1 to register a. operation: (a) iap2 (input accumulator from port p2) 1001100010 262 11 grouping: input/output operation description: transfers the input of port p2 to the low-or- der 2 bits (a 1 , a 0 ) of register a. note: after this instruction is executed, 0 is stored to the high-order 2 bits (a 3 , a 2 ) of register a. operation: (a 1 , a 0 ) operation: (a) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 instructions 1-67 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 iny (increment register y) 0000010011 013 11 (y) = 0 grouping: ram addresses description: adds 1 to the contents of register y. as a re- sult of addition, when the contents of register y is 0, the next instruction is skipped. when the contents of register y is not 0, the next instruction is executed. operation: (y) la n (load n in accumulator) 000111nnnn 07n 11 continuous description grouping: arithmetic operation description: loads the value n in the immediate field to register a. when the la instructions are continuously coded and executed, only the first la in- struction is executed and other la instructions coded continuously are skipped. operation: (a) lxy x, y (load register x and y with x and y) 11x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 3xy 11 continuous description grouping: ram addresses description: loads the value x in the immediate field to register x, and the value y in the immediate field to register y. when the lxy instruc- tions are continuously coded and executed, only the first lxy instruction is executed and other lxy instructions coded continu- ously are skipped. operation: (x) iap3 (input accumulator from port p3) 1001100011 263 11 grouping: input/output operation description: transfers the input of port p3 to the low-or- der 2 bits (a 1 , a 0 ) of register a. note: after this instruction is executed, sets 0 to the high-order 2 bits (a 3 , a 2 ) of register a. operation: (a 1 , a 0 ) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 instructions 1-68 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 lz z (load register z with z) 00010010z 1 z 0 04 11 grouping: ram addresses description: loads the value z in the immediate field to register z. operation: (z) nop (no operation) 0000000000 000 11 grouping: other operation description: no operation; adds 1 to program counter value, and others remain unchanged. operation: (pc) oka (output port k from accumulator) 1000011111 21f 11 grouping: input/output operation description: outputs the contents of bit 0 (a 0 ) of register a to port k. op0a (output port p0 from accumulator) 1000100000 220 11 grouping: input/output operation description: outputs the contents of register a to port p0. operation: (p0) operation: (k) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 instructions 1-69 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 op2a (output port p2 from accumulator) 1000100010 222 11 grouping: input/output operation description: outputs the contents of the low-order 2 bits (a 1 , a 0 ) of register a to port p2. operation: (p2 1 , p2 0 ) op1a (output port p1 from accumulator) 1000100001 221 11 grouping: input/output operation description: outputs the contents of register a to port p1. operation: (p1) or (logical or between accumulator and memory) 0000011001 019 11 grouping: arithmetic operation description: takes the or operation between the con- tents of register a and the contents of m(dp), and stores the result in register a. operation: (a) op3a (output port p3 from accumulator) 1000100011 223 11 grouping: input/output operation description: outputs the contents of the low-order 2 bits (a 1 , a 0 ) of register a to port p3. operation: (p3 1 , p3 0 ) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 instructions 1-70 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 pof (power off1) 0000000010 002 11 grouping: other operation description: puts the system in ram back-up state by executing the pof instruction after execut- ing the epof instruction. however, the voltage drop detection circuit is valid. note: if the epof instruction is not executed before executing this instruction, this instruction is equivalent to the nop instruction. pof2 (power off2) 0000001000 008 11 grouping: other operation description: puts the system in ram back-up state by executing the pof2 instruction after ex- ecuting the epof instruction. operations of all functions are stopped. note: if the epof instruction is not executed before executing this instruction, this instruction is equivalent to the nop instruction. operation: ram back-up operation: ram back-up however, voltage drop detection circuit valid rar (rotate accumulator right) 0000011101 01d 11 0/1 grouping: arithmetic operation description: rotates 1 bit of the contents of register a in- cluding the contents of carry flag cy to the right. operation: rb j (reset bit) 00010011j j 04 11 grouping: bit operation description: clears (0) the contents of bit j (bit specified by the value j in the immediate field) of m(dp). operation: (mj(dp)) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 instructions 1-71 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 rd (reset port d specified by register y) 0000010100 014 11 grouping: input/output operation description: clears (0) to a bit of port d specified by register y. note: set 0 to 5 to register y because port d is six ports (d 0 d 5 ). when values except above are set to regis- ter y, this instruction is equivalent to the nop instruction. operation: (d(y)) rt (return from subroutine) 0001000100 044 12 grouping: return operation description: returns from subroutine to the routine called the subroutine. operation: (pc) 1 rc (reset carry flag) 0000000110 006 11 0 grouping: arithmetic operation description: clears (0) to carry flag cy. operation: (cy) rcp (reset port c) 1010001100 28c 11 grouping: input/output operation description: clears (0) to port c. operation: (c) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 instructions 1-72 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 rti (return from interrupt) 0001000110 046 11 grouping: return operation description: returns from interrupt service routine to main routine. returns each value of data pointer (x, y, z), carry flag, skip status, nop mode status by the continuous description of the la/lxy in- struction, register a and register b to the states just before interrupt. rts (return from subroutine and skip) 0001000101 045 12 skip at uncondition grouping: return operation description: returns from subroutine to the routine called the subroutine, and skips the next in- struction at uncondition. operation: (pc) 1 operation: (pc) 1 sb j (set bit) 00010111j j 05 11 grouping: bit operation description: sets (1) the contents of bit j (bit specified by the value j in the immediate field) of m(dp). operation: (mj(dp)) sc (set carry flag) 0000000111 007 11 1 grouping: arithmetic operation description: sets (1) to carry flag cy. operation: (cy) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 instructions 1-73 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 sea n (skip equal, accumulator with immediate data n) 0000100101 025 22 (a) = n grouping: comparison operation description: skips the next instruction when the con- tents of register a is equal to the value n in the immediate field. executes the next instruction when the con- tents of register a is not equal to the value n in the immediate field. operation: (a) = n ? n = 0 to 15 seam (skip equal, accumulator with memory) 0000100110 026 11 (a) = (m(dp)) grouping: comparison operation description: skips the next instruction when the con- tents of register a is equal to the contents of m(dp). executes the next instruction when the con- tents of register a is not equal to the contents of m(dp). operation: (a) = (m(dp)) ? scp (set port c) 1010001101 28d 11 grouping: input/output operation description: sets (1) to port c. operation: (c) sd (set port d specified by register y) 0000010101 015 11 grouping: input/output operation description: sets (1) to a bit of port d specified by register y. note: set 0 to 5 to register y because port d is six ports (d 0 d 5 ). when values except above are set to regis- ter y, this instruction is equivalent to the nop instruction. operation: (d(y)) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 instructions 1-74 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 snz0 (skip if non zero condition of external 0 interrupt request flag) 0000111000 038 11 v1 0 = 0: (exf0) = 1 grouping: interrupt operation description: when v1 0 = 0 : skips the next instruction when external 0 interrupt request flag exf0 is 1. after skipping, clears (0) to the exf0 flag. when the exf0 flag is 0, executes the next instruction. when v1 0 = 1 : this instruction is equiva- lent to the nop instruction. operation: v1 0 = 0: (exf0) = 1 ? after skipping, (exf0) snzcp (skip if non zero condition of port c) 1010001001 289 11 (c) = 1 grouping: input/output operation description: skips the next instruction when the con- tents of port c is 1. executes the next instruction when the con- tents of port c is 0. operation: (c) = 1 ? snzad (skip if non zero condition of a/d conversion completion flag) 1010000111 287 11 v2 2 = 0: (adf) = 1 grouping: a/d conversion operation description: when v2 2 = 0 : skips the next instruction when a/d conversion completion flag adf is 1. after skipping, clears (0) to the adf flag. when the adf flag is 0, executes the next instruction. when v2 2 = 1 : this instruction is equiva- lent to the nop instruction. operation: v2 2 = 0: (adf) = 1 ? after skipping, (adf) snzi0 (skip if non zero condition of external 0 interrupt input pin) 0000111010 03a 11 i1 2 = 0 : (int) = l i1 2 = 1 : (int) = h grouping: interrupt operation description: when i1 2 = 0 : skips the next instruction when the level of int pin is l. executes the next instruction when the level of int pin is h. when i1 2 = 1 : skips the next instruction when the level of int pin is h. executes the next instruction when the level of int pin is l. operation: i1 2 = 0 : (int) = l ? i1 2 = 1 : (int) = h ? (i1 2 : bit 2 of the interrupt control register i1) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 instructions 1-75 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 szb j (skip if zero, bit) 00001000j j 02j 11 (mj(dp)) = 0 j = 0 to 3 grouping: bit operation description: skips the next instruction when the con- tents of bit j (bit specified by the value j in the immediate field) of m(dp) is 0. executes the next instruction when the con- tents of bit j of m(dp) is 1. operation: (mj(dp)) = 0 ? j = 0 to 3 snzp (skip if non zero condition of power down flag) 0000000011 003 11 (p) = 1 grouping: other operation description: skips the next instruction when the p flag is 1 . after skipping, the p flag remains un- changed. executes the next instruction when the p flag is 0. snzt1 (skip if non zero condition of timer 1 inerrupt request flag) 1010000000 280 11 v1 2 = 0: (t1f) = 1 grouping: timer operation description: when v1 2 = 0 : skips the next instruction when timer 1 interrupt request flag t1f is 1. after skipping, clears (0) to the t1f flag. when the t1f flag is 0, executes the next instruction. when v1 2 = 1 : this instruction is equiva- lent to the nop instruction. operation: v1 2 = 0: (t1f) = 1 ? after skipping, (t1f) snzt2 (skip if non zero condition of timer 2 inerrupt request flag) 1010000001 281 11 v1 3 = 0: (t2f) = 1 grouping: timer operation description: when v1 3 = 0 : skips the next instruction when timer 2 interrupt request flag t2f is 1. after skipping, clears (0) to the t2f flag. when the t2f flag is 0, executes the next instruction. when v1 3 = 1 : this instruction is equiva- lent to the nop instruction. operation: v1 3 = 0: (t2f) = 1 ? after skipping, (t2f) operation: (p) = 1 ? machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 instructions 1-76 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 szc (skip if zero, carry flag) 0000101111 02f 11 (cy) = 0 grouping: arithmetic operation description: skips the next instruction when the con- tents of carry flag cy is 0. after skipping, the cy flag remains un- changed. executes the next instruction when the con- tents of the cy flag is 1. operation: (cy) = 0 ? szd (skip if zero, port d specified by register y) 0000100100 024 22 (d(y)) = 0 (y) = 0 to 5 grouping: input/output operation description: skips the next instruction when a bit of port d specified by register y is 0. executes the next instruction when the bit is 1. note: set 0 to 5 to register y because port d is six ports (d 0 d 5 ). when values except above are set to register y, this instruction is equivalent to the nop instruction. t1ab (transfer data to timer 1 and register r1 from accumulator and register b) 1000110000 230 11 grouping: timer operation description: transfers the contents of register b to the high-order 4 bits of timer 1 and timer 1 re- load register r1. transfers the contents of register a to the low-order 4 bits of timer 1 and timer 1 reload register r1. operation: (t1 7 t1 4 ) r1 4 ) t1 0 ) r1 0 ) operation: (d(y)) = 0 ? (y) = 0 to 5 2 16 0000101011 02b t2ab (transfer data to timer 2 and register r2 from accumulator and register b) 1000110001 231 11 grouping: timer operation description: transfers the contents of register b to the high-order 4 bits of timer 2 and timer 2 re- load register r2. transfers the contents of register a to the low-order 4 bits of timer 2 and timer 2 reload register r2. operation: (t2 7 t2 4 ) r2 4 ) t2 0 ) r2 0 ) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 instructions 1-77 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 tab (transfer data to accumulator from register b) 0000011110 01e 11 grouping: other operation description: transfers the contents of register b to reg- ister a. tab1 (transfer data to accumulator and register b from timer 1) 1001110000 270 11 grouping: timer operation description: transfers the high-order 4 bits (t1 7 t1 4 ) of timer 1 to register b. transfers the low-order 4 bits (t1 3 t1 0 ) of timer 1 to register a. operation: (b) t1 4 ) (a) t1 0 ) tab2 (transfer data to accumulator and register b from timer 2) 1001110001 271 11 grouping: timer operation description: transfers the high-order 4 bits (t2 7 t2 4 ) of timer 2 to register b. transfers the low-order 4 bits (t2 3 t2 0 ) of timer 2 to register a. operation: (b) t2 4 ) (a) t2 0 ) operation: (a) tabad (transfer data to accumulator and register b from register ad) 1001111001 279 11 grouping: a/d conversion operation description: in the a/d conversion mode (q1 3 = 0), trans- fers the high-order 4 bits (ad 9 ad 6 ) of register ad to register b, and the middle-order 4 bits (ad 5 ad 2 ) of register ad to register a. in the comparator mode (q1 3 = 1), transfers the high- order 4 bits (ad 7 ad 4 ) of comparator register to register b, and the low-order 4 bits (ad 3 ad 0 ) of comparator register to register a. operation: in a/d conversion mode (q1 3 = 0), (b) ad 6 ) (a) ad 2 ) in comparator mode (q1 3 = 1), (b) ad 4 ) (a) ad 0 ) (q1 3 : bit 3 of a/d control register q1) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 instructions 1-78 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 tabe (transfer data to accumulator and register b from register e) 0000101010 02a 11 grouping: register to register transfer description: transfers the high-order 4 bits (e 7 e 4 ) of register e to register b, and low-order 4 bits of register e to register a. operation: (b) e 4 ) (a) e 0 ) tabp p (transfer data to accumulator and register b from program memory in page p) 00100p 4 p 3 p 2 p 1 p 0 0p 13 grouping: arithmetic operation description: transfers bits 7 to 4 to register b and bits 3 to 0 to register a. these bits 7 to 0 are the rom pattern in ad-dress (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers a and d in page p. note: p is 0 to 15 for m34502m2, and p is 0 to 31 for m34502m4/e4. when this instruction is executed, be careful not to over the stack because 1 stage of stack register is used. operation: (sp) dr 0 , a 3 a 0 ) (b) 4 (a) 0 (pc) 1 tad (transfer data to accumulator from register d) 0001010001 051 11 grouping: register to register transfer description: transfers the contents of register d to the low-order 3 bits (a 2 a 0 ) of register a. note: when this instruction is executed, 0 is stored to the bit 3 (a 3 ) of register a. tadab (transfer data to register ad from accumulator from register b) 1000111001 239 11 grouping: a/d conversion operation description: in the a/d conversion mode (q1 3 = 0), this in- struction is equivalent to the nop instruction. in the comparator mode (q1 3 = 1), trans- fers the contents of register b to the high-order 4 bits (ad 7 ad 4 ) of comparator register, and the contents of register a to the low-order 4 bits (ad 3 ad 0 ) of compara- tor register. (q1 3 = bit 3 of a/d control register q1) operation: (ad 7 ad 4 ) ad 0 ) operation: (a 2 a 0 ) dr 0 ) (a 3 ) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 instructions 1-79 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 tai1 (transfer data to accumulator from register i1) 1001010011 253 11 grouping: interrupt operation description: transfers the contents of interrupt control register i1 to register a. operation: (a) tak0 (transfer data to accumulator from register k0) 1001010110 256 11 grouping: input/output operation description: transfers the contents of key-on wakeup control register k0 to register a. operation: (a) tak1 (transfer data to accumulator from register k1) 1001011001 259 11 grouping: input/output operation description: transfers the contents of key-on wakeup control register k1 to register a. operation: (a) tak2 (transfer data to accumulator from register k2) 1001011010 25a 11 grouping: input/output operation description: transfers the contents of key-on wakeup control register k2 to register a. operation: (a) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 instructions 1-80 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 tala (transfer data to accumulator from register la) 1001001001 249 11 grouping: a/d conversion operation description: transfers the low-order 2 bits (ad 1 , ad 0 ) of register ad to the high-order 2 bits (a 3 , a 2 ) of register a. note: after this instruction is executed, 0 is stored to the low-order 2 bits (a 1 , a 0 ) of register a. operation: (a 3 , a 2 ) tam j (transfer data to accumulator from memory) 101100 jjjj 2cj 11 grouping: ram to register transfer description: after transferring the contents of m(dp) to register a, an exclusive or operation is performed between register x and the value j in the immediate field, and stores the re- sult in register x. tamr (transfer data to accumulator from register mr) 1001010010 252 11 grouping: other operation description: transfers the contents of clock control reg- ister mr to register a. operation: (a) operation: (a) taq1 (transfer data to accumulator from register q1) 1001000100 244 11 grouping: a/d conversion operation description: transfers the contents of a/d control regis- ter q1 to register a. operation: (a) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 instructions 1-81 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 tasp (transfer data to accumulator from stack pointer) 0001010000 050 11 grouping: register to register transfer description: transfers the contents of stack pointer (sp) to the low-order 3 bits (a 2 a 0 ) of register a. note: after this instruction is executed, 0 is stored to the bit 3 (a 3 ) of register a. tav1 (transfer data to accumulator from register v1) 0001010100 054 11 grouping: interrupt operation description: transfers the contents of interrupt control register v1 to register a. operation: (a) tav2 (transfer data to accumulator from register v2) 0001010101 055 11 grouping: interrupt operation description: transfers the contents of interrupt control register v2 to register a. operation: (a) taw1 (transfer data to accumulator from register w1) 1001001011 24b 11 grouping: timer operation description: transfers the contents of timer control reg- ister w1 to register a. operation: (a) operation: (a 2 a 0 ) sp 0 ) (a 3 ) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 instructions 1-82 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 taw2 (transfer data to accumulator from register w2) 1001001100 24c 11 grouping: timer operation description: transfers the contents of timer control reg- ister w2 to register a. operation: (a) taw6 (transfer data to accumulator from register w6) 1001010000 250 11 grouping: timer operation description: transfers the contents of timer control reg- ister w6 to register a. tax (transfer data to accumulator from register x) 0001010010 052 11 grouping: register to register transfer description: transfers the contents of register x to reg- ister a. operation: (a) operation: (a) tay (transfer data to accumulator from register y) 0000011111 01f 11 grouping: register to register transfer description: transfers the contents of register y to regis- ter a. operation: (a) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 instructions 1-83 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 tba (transfer data to register b from accumulator) 0000001110 00e 11 grouping: register to register transfer description: transfers the contents of register a to regis- ter b. tda (transfer data to register d from accumulator) 0000101001 029 11 grouping: register to register transfer description: transfers the contents of the low-order 3 bits (a 2 a 0 ) of register a to register d. operation: (dr 2 dr 0 ) a 0 ) teab (transfer data to register e from accumulator and register b) 0000011010 01a 11 grouping: register to register transfer description: transfers the contents of register b to the high-order 4 bits (e 3 e 0 ) of register e, and the contents of register a to the low-order 4 bits (e 3 e 0 ) of register e. operation: (e 7 e 4 ) e 0 ) operation: (b) taz (transfer data to accumulator from register z) 0001010011 053 11 grouping: register to register transfer description: transfers the contents of register z to the low-order 2 bits (a 1 , a 0 ) of register a. note: after this instruction is executed, 0 is stored to the high-order 2 bits (a 3 , a 2 ) of register a. operation: (a 1 , a 0 ) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 instructions 1-84 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 ti1a (transfer data to register i1 from accumulator) 1000010111 217 11 grouping: interrupt operation description: transfers the contents of register a to inter- rupt control register i1. operation: (i1) tk0a (transfer data to register k0 from accumulator) 1000011011 21b 11 grouping: input/output operation description: transfers the contents of register a to key- on wakeup control register k0. operation: (k0) tk1a (transfer data to register k1 from accumulator) 1000010100 214 11 grouping: input/output operation description: transfers the contents of register a to key- on wakeup control register k1. tk2a (transfer data to register k2 from accumulator) 1000010101 215 11 grouping: input/output operation description: transfers the contents of register a to key- on wakeup control register k2. operation: (k2) operation: (k1) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 instructions 1-85 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 tma j (transfer data to memory from accumulator) 101011 jjjj 2bj 11 grouping: ram to register transfer description: after transferring the contents of register a to m(dp), an exclusive or operation is per- formed between register x and the value j in the immediate field, and stores the result in register x. operation: (m(dp)) tmra (transfer data to register mr from accumulator) 1000010110 216 11 grouping: other operation description: transfers the contents of register a to clock control register mr. tpu0a (transfer data to register pu0 from accumulator) 1000101101 22d 11 grouping: input/output operation description: transfers the contents of register a to pull- up control register pu0. operation: (pu0) tpu1a (transfer data to register pu1 from accumulator) 1000101110 22e 11 grouping: input/output operation description: transfers the contents of register a to pull- up control register pu1. operation: (pu1) operation: (mr) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 instructions 1-86 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 tq1a (transfer data to register q1 from accumulator) 1000000100 204 11 grouping: a/d conversion operation description: transfers the contents of register a to a/d control register q1. operation: (q1) tr1ab (transfer data to register r1 from accumulator and register b) 1000111111 23f 11 grouping: timer operation description: transfers the contents of register b to the high-order 4 bits (r1 7 r1 4 ) of reload regis- ter r1, and the contents of register a to the low-order 4 bits (r1 3 r1 0 ) of reload regis- ter r1. tv1a (transfer data to register v1 from accumulator) 0000111111 03f 11 grouping: interrupt operation description: transfers the contents of register a to inter- rupt control register v1. operation: (v1) operation: (r1 7 r1 4 ) r1 0 ) tpu2a (transfer data to register pu2 from accumulator) 1000101111 22f 11 grouping: input/output operation description: transfers the contents of register a to pull- up control register pu2. operation: (pu2) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 instructions 1-87 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 tw1a (transfer data to register w1 from accumulator) 1000001110 20e 11 grouping: timer operation description: transfers the contents of register a to timer control register w1. operation: (w1) tv2a (transfer data to register v2 from accumulator) 0000111110 03e 11 grouping: interrupt operation description: transfers the contents of register a to inter- rupt control register v2. operation: (v2) tw2a (transfer data to register w2 from accumulator) 1000001111 20f 11 grouping: timer operation description: transfers the contents of register a to timer control register w2. operation: (w2) tw6a (transfer data to register w6 from accumulator) 1000010011 213 11 grouping: timer operation description: transfers the contents of register a to timer control register w6. operation: (w6) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 instructions 1-88 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 tya (transfer data to register y from accumulator) 0000001100 00c 11 grouping: register to register transfer description: transfers the contents of register a to regis- ter y. operation: (y) wrst (watchdog timer reset) 1010100000 2a0 11 (wdf1) = 1 grouping: other operation description: skips the next instruction when watchdog timer flag wdf1 is 1. after skipping, clears (0) to the wdf1 flag. when the wdf1 flag is 0, executes the next instruction. also, stops the watchdog timer function when ex- ecuting the wrst instruction immediately after the dwdt instruction. operation: (wdf1) = 1 ? after skipping, (wdf1) xam j (exchange accumulator and memory data) 101101 jjjj 2dj 11 grouping: ram to register transfer description: after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is performed between regis- ter x and the value j in the immediate field, and stores the result in register x. xamd j (exchange accumulator and memory data and decrement register y and skip) 101111 jjjj 2fj 11 (y) = 15 grouping: ram to register transfer description: after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is performed between regis- ter x and the value j in the immediate field, and stores the result in register x. subtracts 1 from the contents of register y. as a result of subtraction, when the con- tents of register y is 15, the next instruction is skipped. when the contents of register y is not 15, the next instruction is executed. operation: (a) 1 operation: (a) machine instructions (index by alphabet) (continued)
xami j (exchange accumulator and memory data and increment register y and skip) 101110 jjjj 2ej 11 (y) = 0 grouping: ram to register transfer description: after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is performed between regis- ter x and the value j in the immediate field, and stores the result in register x. adds 1 to the contents of register y. as a re- sult of addition, when the contents of register y is 0, the next instruction is skipped. when the contents of register y is not 0, the next instruction is executed. operation: (a) (m(dp)) (x) (x)exor(j) j = 0 to 15 (y) (y) + 1 skip condition number of cycles number of words instruction code d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 flag cy 2 16 machine instructions (index by alphabet) (continued) skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 instructions 1-89 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201
parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation instructions 1-90 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 (a) e 4 ) e 0 ) e 4 ) (a) e 0 ) (dr 2 dr 0 ) a 0 ) (a 2 a 0 ) dr 0 ) (a 3 ) a 0 ) sp 0 ) (a 3 ) 1 (a) 1 (a) machine instructions (index by types) 0000011110 0000001110 0000011111 0000001100 0000011010 0000101010 0000101001 0001010001 0001010011 0001010010 0001010000 11x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 00010010z 1 z 0 0000010011 0000010111 101100 jjjj 101101 jjjj 101111 jjjj 101110 jjjj 101011 jjjj 01e 00e 01f 00c 01a 02a 029 051 053 052 050 3xy 048 +z 013 017 2cj 2dj 2fj 2ej 2bj 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ram addresses ram to register transfer register to register transfer
skip condition datailed description carry flag cy instructions 1-91 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 continuous description (y) = 0 (y) = 15 (y) = 15 (y) = 0 transfers the contents of register b to register a. transfers the contents of register a to register b. transfers the contents of register y to register a. transfers the contents of register a to register y. transfers the contents of register b to the high-order 4 bits (e 3 e 0 ) of register e, and the contents of regis- ter a to the low-order 4 bits (e 3 e 0 ) of register e. transfers the high-order 4 bits (e 7 e 4 ) of register e to register b, and low-order 4 bits of register e to regis- ter a. transfers the contents of the low-order 3 bits (a 2 a 0 ) of register a to register d. transfers the contents of register d to the low-order 3 bits (a 2 a 0 ) of register a. transfers the contents of register z to the low-order 2 bits (a 1 , a 0 ) of register a. transfers the contents of register x to register a. transfers the contents of stack pointer (sp) to the low-order 3 bits (a 2 a 0 ) of register a. loads the value x in the immediate field to register x, and the value y in the immediate field to register y. when the lxy instructions are continuously coded and executed, only the first lxy instruction is executed and other lxy instructions coded continuously are skipped. loads the value z in the immediate field to register z. adds 1 to the contents of register y. as a result of addition, when the contents of register y is 0, the next in- struction is skipped. when the contents of register y is not 0, the next instruction is executed. subtracts 1 from the contents of register y. as a result of subtraction, when the contents of register y is 15, the next instruction is skipped. when the contents of register y is not 15, the next instruction is executed. after transferring the contents of m(dp) to register a, an exclusive or operation is performed between reg- ister x and the value j in the immediate field, and stores the result in register x. after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is per- formed between register x and the value j in the immediate field, and stores the result in register x. after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is per- formed between register x and the value j in the immediate field, and stores the result in register x. subtracts 1 from the contents of register y. as a result of subtraction, when the contents of register y is 15, the next instruction is skipped. when the contents of register y is not 15, the next instruction is executed. after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is per- formed between register x and the value j in the immediate field, and stores the result in register x. adds 1 to the contents of register y. as a result of addition, when the contents of register y is 0, the next in- struction is skipped. when the contents of register y is not 0, the next instruction is executed. after transferring the contents of register a to m(dp), an exclusive or operation is performed between reg- ister x and the value j in the immediate field, and stores the result in register x.
parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation instructions 1-92 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 note : p is 0 to 15 for m34502m2, p is 0 to 31 for m34502m4/e4. machine instructions (index by types) (continued) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 07n 08p +p 00a 00b 06n 018 019 007 006 02f 01c 01d 05c +j 04c +j 02j 026 025 07n 000111nnnn 00100p 4 p 3 p 2 p 1 p 0 0000001010 0000001011 000110nnnn 0000011000 0000011001 0000000111 0000000110 0000101111 0000011100 0000011101 00010111j j 00010011j j 00001000j j 0000100110 0000100101 000111nnnn la n tabp p am amc a n and or sc rc szc cma rar sb j rb j szb j seam sea n 1 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 arithmetic operation comparison operation bit operation (a) dr 0 , a 3 a 0 ) (b) 4 (a) 0 (pc) 1 (a)
skip condition datailed description carry flag cy instructions 1-93 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 continuous description overflow = 0 (cy) = 0 (mj(dp)) = 0 j = 0 to 3 (a) = (m(dp)) (a) = n 0/1 1 0 0/1 loads the value n in the immediate field to register a. when the la instructions are continuously coded and executed, only the first la instruction is executed and other la instructions coded continuously are skipped. transfers bits 7 to 4 to register b and bits 3 to 0 to register a. these bits 7 to 0 are the rom pattern in ad- dress (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers a and d in page p. when this instruction is executed, be careful not to over the stack because 1 stage of stack register is used. adds the contents of m(dp) to register a. stores the result in register a. the contents of carry flag cy re- mains unchanged. adds the contents of m(dp) and carry flag cy to register a. stores the result in register a and carry flag cy. adds the value n in the immediate field to register a, and stores a result in register a. the contents of carry flag cy remains unchanged. skips the next instruction when there is no overflow as the result of operation. executes the next instruction when there is overflow as the result of operation. takes the and operation between the contents of register a and the contents of m(dp), and stores the re- sult in register a. takes the or operation between the contents of register a and the contents of m(dp), and stores the result in register a. sets (1) to carry flag cy. clears (0) to carry flag cy. skips the next instruction when the contents of carry flag cy is 0. stores the one s complement for register a s contents in register a. rotates 1 bit of the contents of register a including the contents of carry flag cy to the right. sets (1) the contents of bit j (bit specified by the value j in the immediate field) of m(dp). clears (0) the contents of bit j (bit specified by the value j in the immediate field) of m(dp). skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of m(dp) is 0. executes the next instruction when the contents of bit j of m(dp) is 1. skips the next instruction when the contents of register a is equal to the contents of m(dp). executes the next instruction when the contents of register a is not equal to the contents of m(dp). skips the next instruction when the contents of register a is equal to the value n in the immediate field. executes the next instruction when the contents of register a is not equal to the value n in the immediate field.
parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation instructions 1-94 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 b a bl p, a bla p bm a bml p, a bmla p rti rt rts 011a 6 a 5 a 4 a 3 a 2 a 1 a 0 00111p 4 p 3 p 2 p 1 p 0 100a 6 a 5 a 4 a 3 a 2 a 1 a 0 0000010000 100p 4 00p 3 p 2 p 1 p 0 010a 6 a 5 a 4 a 3 a 2 a 1 a 0 00110p 4 p 3 p 2 p 1 p 0 100a 6 a 5 a 4 a 3 a 2 a 1 a 0 0000110000 100p 4 00p 3 p 2 p 1 p 0 0001000110 0001000100 0001000101 18a +a 0ep +p 2aa 010 2pp 1aa 0cp +p 2aa 030 2pp 046 044 045 1 2 2 1 2 2 1 1 1 1 2 2 1 2 2 1 2 2 subroutine operation return operation machine instructions (continued) (pc l ) a 0 (pc h ) a 0 (pc h ) dr 0 , a 3 a 0 ) (sp) a 0 (sp) a 0 (sp) dr 0 ,a 3 a 0 ) (pc) 1 (pc) 1 (pc) 1 branch operation note : p is 0 to 15 for m34502m2, p is 0 to 31 for m34502m4/e4.
skip condition datailed description carry flag cy instructions 1-95 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 skip at uncondition branch within a page : branches to address a in the identical page. branch out of a page : branches to address a in page p. branch out of a page : branches to address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers d and a in page p. call the subroutine in page 2 : calls the subroutine at address a in page 2. call the subroutine : calls the subroutine at address a in page p. call the subroutine : calls the subroutine at address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers d and a in page p. returns from interrupt service routine to main routine. returns each value of data pointer (x, y, z), carry flag, skip status, nop mode status by the continuous de- scription of the la/lxy instruction, register a and register b to the states just before interrupt. returns from subroutine to the routine called the subroutine. returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.
di ei snz0 snzi0 tav1 tv1a tav2 tv2a tai1 ti1a taw1 tw1a taw2 tw2a taw6 tw6a tab1 t1ab tab2 t2ab tr1ab snzt1 snzt2 (inte) 0 (inte) 1 v1 0 = 0: (exf0) = 1 ? after skipping, (exf0) 0 v1 0 = 1: snz0 = nop i1 2 = 0 : (int) = ??? i1 2 = 1 : (int) = ??? (a) (v1) (v1) (a) (a) (v2) (v2) (a) (a) (i1) (i1) (a) (a) (w1) (w1) (a) (a) (w2) (w2) (a) (a) (w6) (w6) (a) (b) (t1 7 ?1 4 ) (a) (t1 3 ?1 0 ) (t1 7 ?1 4 ) (b) (r1 7 ?1 4 ) (b) (t1 3 ?1 0 ) (a) (r1 3 ?1 0 ) (a) (b) (t2 7 ?2 4 ) (a) (t2 3 ?2 0 ) (t2 7 ?2 4 ) (b) (r2 7 ?2 4 ) (b) (t2 3 ?2 0 ) (a) (r2 3 ?2 0 ) (a) (r1 7 ?1 4 ) (b) (r1 3 ?1 0 ) (a) v1 2 = 0: (t1f) = 1 ? after skipping, (t1f) 0 v1 2 = 1: snzt1 = nop v1 3 = 0: (t2f) = 1 ? after skipping, (t2f) 0 v1 3 = 1: snzt2 = nop 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 004 005 038 03a 054 03f 055 03e 253 217 24b 20e 24c 20f 250 213 270 230 271 231 23f 280 281 0000000100 0000000101 0000111000 0000111010 0001010100 0000111111 0001010101 0000111110 1001010011 1000010111 1001001011 1000001110 1001001100 1000001111 1001010000 1000010011 1001110000 1000110000 1001110001 1000110001 1000111111 1010000000 1010000001 interrupt operation timer operation parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation machine instructions (index by types) (continued) instructions 1-96 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201
v1 0 = 0: (exf0) = 1 (int) = ? however, i1 2 = 0 (int) = ? however, i1 2 = 1 v1 2 = 0: (t1f) = 1 v1 3 = 0: (t2f) =1 skip condition datailed description carry flag cy clears (0) to interrupt enable flag inte, and disables the interrupt. sets (1) to interrupt enable flag inte, and enables the interrupt. when v1 0 = 0 : skips the next instruction when external 0 interrupt request flag exf0 is ?.?after skipping, clears (0) to the exf0 flag. when the exf0 flag is ?,?executes the next instruction. when v1 0 = 1 : this instruction is equivalent to the nop instruction. (v1 0 : bit 0 of interrupt control register v1) when i1 2 = 0 : skips the next instruction when the level of int pin is ?.?executes the next instruction when the level of int pin is ?. when i1 2 = 1 : skips the next instruction when the level of int pin is ?.?executes the next instruction when the level of int pin is ?.?(i1 2 : bit 2 of interrupt control register i1) transfers the contents of interrupt control register v1 to register a. transfers the contents of register a to interrupt control register v1. transfers the contents of interrupt control register v2 to register a. transfers the contents of register a to interrupt control register v2. transfers the contents of interrupt control register i1 to register a. transfers the contents of register a to interrupt control register i1. transfers the contents of timer control register w1 to register a. transfers the contents of register a to timer control register w1. transfers the contents of timer control register w2 to register a. transfers the contents of register a to timer control register w2. transfers the contents of timer control register w6 to register a. transfers the contents of register a to timer control register w6. transfers the high-order 4 bits (t1 7 ?1 4 ) of timer 1 to register b. transfers the low-order 4 bits (t1 3 ?1 0 ) of timer 1 to register a. transfers the contents of register b to the high-order 4 bits of timer 1 and timer 1 reload register r1. trans- fers the contents of register a to the low-order 4 bits of timer 1 and timer 1 reload register r1. transfers the high-order 4 bits (t2 7 ?2 4 ) of timer 2 to register b. transfers the low-order 4 bits (t2 3 ?2 0 ) of timer 2 to register a. transfers the contents of register b to the high-order 4 bits of timer 2 and timer 2 reload register r2. trans- fers the contents of register a to the low-order 4 bits of timer 2 and timer 2 reload register r2. transfers the contents of register b to the high-order 4 bits (r1 7 ?1 4 ) of reload register r1, and the con- tents of register a to the low-order 4 bits (r1 3 ?1 0 ) of reload register r1. when v1 2 = 0 : skips the next instruction when timer 1 interrupt request flag t1f is ?.?after skipping, clears (0) to the t1f flag. when the t1f flag is ?,?executes the next instruction. when v1 2 = 1 : this instruction is equivalent to the nop instruction. (v1 2 : bit 2 of interrupt control register v1) when v1 3 = 0 : skips the next instruction when timer 1 interrupt request flag t2f is ?.?after skipping, clears (0) to the t2f flag. when the t2f flag is ?,?executes the next instruction. when v1 3 = 1 : this instruction is equivalent to the nop instruction. (v1 3 : bit 3 of interrupt control register v1) instructions 1-97 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201
parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation instructions 1-98 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 iap0 op0a iap1 op1a iap2 op2a iap3 op3a cld rd sd szd scp rcp snzcp iak oka tk0a tak0 tk1a tak1 tk2a tak2 tpu0a tpu1a tpu2a 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 260 220 261 221 262 222 263 223 011 014 015 024 02b 28d 28c 289 26f 21f 21b 256 214 259 215 25a 22d 22e 22f 1001100000 1000100000 1001100001 1000100001 1001100010 1000100010 1001100011 1000100011 0000010001 0000010100 0000010101 0000100100 0000101011 1010001101 1010001100 1010001001 1001101111 1000011111 1000011011 1001010110 1000010100 1001011001 1000010101 1001011010 1000101101 1000101110 1000101111 input/output operation (a) a 1 ) machine instructions (index by types) (continued)
skip condition datailed description carry flag cy instructions 1-99 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 (d(y)) = 0 ? (y) = 0 to 5 (c) = 1 transfers the input of port p0 to register a. outputs the contents of register a to port p0. transfers the input of port p1 to register a. outputs the contents of register a to port p1. transfers the input of port p2 to the low-order 2 bits (a 1 , a 0 ) of register a. outputs the contents of the low-order 2 bits (a 1 , a 0 ) of register a to port p2. transfers the input of port p3 to the low-order 2 bits (a 1 , a 0 ) of register a. outputs the contents of the low-order 2 bits (a 1 , a 0 ) of register a to port p3. sets (1) to port d. clears (0) to a bit of port d specified by register y. sets (1) to a bit of port d specified by register y. skips the next instruction when a bit of port d specified by register y is 0. executes the next instruction when a bit of port d specified by register y is 1. sets (1) to port c. clears (0) to port c. skips the next instruction when the contents of port c is 1. executes the next instruction when the contents of port c is 0. transfers the contents of port k to the bit 0 (a 0 ) of register a. outputs the contents of bit 0 (a 0 ) of register a to port k. transfers the contents of register a to key-on wakeup control register k0. transfers the contents of key-on wakeup control register k0 to register a. transfers the contents of register a to key-on wakeup control register k1. transfers the contents of key-on wakeup control register k1 to register a. transfers the contents of register a to key-on wakeup control register k2. transfers the contents of key-on wakeup control register k2 to register a. transfers the contents of register a to pull-up control register pu0. transfers the contents of register a to pull-up control register pu1. transfers the contents of register a to pull-up control register pu2.
parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation instructions 1-100 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 tabad tala tadab taq1 tq1a adst snzad nop pof pof2 epof snzp dwdt wrst cmck crck tamr tmra 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 279 249 239 244 204 29f 287 000 002 008 05b 003 29c 2a0 29a 29b 252 216 1001111001 1001001001 1000111001 1001000100 1000000100 1010011111 1010000111 0000000000 0000000010 0000001000 0001011011 0000000011 1010011100 1010100000 1010011010 1010011011 1001010010 1000010110 a/d conversion operation other operation in a/d conversion mode (q1 3 = 0), (b) ad 6 ) (a) ad 2 ) in comparator mode (q1 3 = 1), (b) ad 4 ) (a) ad 0 ) (a 3 , a 2 ) ad 4 ) ad 0 ) machine instructions (index by types) (continued)
skip condition datailed description carry flag cy instructions 1-101 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 v2 2 = 0: (adf) = 1 (p) = 1 (wdf1) = 1 in the a/d conversion mode (q1 3 = 0), transfers the high-order 4 bits (ad 9 ad 6 ) of register ad to register b, and the middle-order 4 bits (ad 5 ad 2 ) of register ad to register a. in the comparator mode (q1 3 = 1), transfers the high-order 4 bits (ad 7 ad 4 ) of comparator register to reg- ister b, and the low-order 4 bits (ad 3 ad 0 ) of comparator register to register a. (q1 3 : bit 3 of a/d control register q1) transfers the low-order 2 bits (ad 1 , ad 0 ) of register ad to the high-order 2 bits (ad 3 , ad 2 ) of register a. in the a/d conversion mode (q1 3 = 0), this instruction is equivalent to the nop instruction. in the comparator mode (q1 3 = 1), transfers the contents of register b to the high-order 4 bits (ad 7 ad 4 ) of comparator register, and the contents of register a to the low-order 4 bits (ad 3 ad 0 ) of comparator register. (q1 3 = bit 3 of a/d control register q1) transfers the contents of a/d control register q1 to register a. transfers the contents of register a to a/d control register q1. clears (0) to a/d conversion completion flag adf, and the a/d conversion at the a/d conversion mode (q1 3 = 0) or the comparator operation at the comparator mode (q1 3 = 1) is started. (q1 3 = bit 3 of a/d control register q1) when v2 2 = 0 : skips the next instruction when a/d conversion completion flag adf is 1. after skipping, clears (0) to the adf flag. when the adf flag is 0, executes the next instruction. when v2 2 = 1 : this instruction is equivalent to the nop instruction. (v2 2 : bit 2 of interrupt control register v2) no operation; adds 1 to program counter value, and others remain unchanged. puts the system in ram back-up state by executing the pof instruction after executing the epof instruc- tion. however, the voltage drop detection circuit is valid. puts the system in ram back-up state by executing the pof2 instruction after executing the epof instruction. operations of all functions are stopped. makes the immediate after pof or pof2 instruction valid by executing the epof instruction. skips the next instruction when the p flag is 1 . after skipping, the p flag remains unchanged. executes the next instruction when the p flag is 0. stops the watchdog timer function by the wrst instruction after executing the dwdt instruction. skips the next instruction when watchdog timer flag wdf1 is 1. after skipping, clears (0) to the wdf1 flag. when the wdf1 flag is 0, executes the next instruction. also, stops the watchdog timer function when ex- ecuting the wrst instruction immediately after the dwdt instruction. selects the ceramic resonance circuit and stops the on-chip oscillator. selects the rc oscillation circuit and stops the on-chip oscillator. transfers the contents of clock control register mr to register a. transfers the contents of register a to clock control register mr.
1-102 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 instruction code table d 3 d 0 hex. notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 a b c d e f d 9 d 4 00 nop pof snzp di ei rc sc pof2 am amc tya tba 000001 01 bla cld iny rd sd dey and or teab cma rar tab tay 000010 02 szb 0 szb 1 szb 2 szb 3 szd sean seam tda tabe szc 000011 03 bmla snz0 snzi0 tv2a tv1a 000100 04 rt rts rti lz 0 lz 1 lz 2 lz 3 rb 0 rb 1 rb 2 rb 3 000101 05 tasp tad tax taz tav1 tav2 epof sb 0 sb 1 sb 2 sb 3 000110 06 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 000111 07 la 0 la 1 la 2 la 3 la 4 la 5 la 6 la 7 la 8 la 9 la 10 la 11 la 12 la 13 la 14 la 15 001000 08 tabp 0 tabp 1 tabp 2 tabp 3 tabp 4 tabp 5 tabp 6 tabp 7 tabp 8 tabp 9 tabp 10 tabp 11 tabp 12 tabp 13 tabp 14 tabp 15 001001 09 tabp 16* tabp 17* tabp 18* tabp 19* tabp 20* tabp 21* tabp 22* tabp 23* tabp 24* tabp 25* tabp 26* tabp 27* tabp 28* tabp 29* tabp 30* tabp 31* 001010 0a 001011 0b 001100 0c 001101 0d 001110 0e 001111 0f bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml* bml* bml* bml* bml* bml* bml* bml* bml* bml* bml* bml* bml* bml* bml* bml* bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl* bl* bl* bl* bl* bl* bl* bl* bl* bl* bl* bl* bl* bl* bl* bl* bm bm bm bm bm bm bm bm bm bm bm bm bm bm bm bm 010000 010111 011000 011111 18 1f b b b b b b b b b b b b b b b b bl bml bla bmla sea szd the second word 10 0aaa aaaa 10 0aaa aaaa 10 0p00 pppp 10 0p00 pppp 00 0111 nnnn 00 0010 1011 * cannot be used in the M34502M2-XXXFP. 10 17 000000 the above table shows the relationship between machine language codes and machine language instructions. d 3 d 0 show the low-order 4 bits of the machine language code, and d 9 d 4 show the high-order 6 bits of the machine language code. the hexadecimal representa- tion of the code is also provided. there are one-word instructions and two-word instructions, but only the first word of each i nstruction is shown. do not use code marked . the codes for the second word of a two-word instruction are described below. instructions
1-103 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 instruction code table (continued) tq1a tw1a tw2a tw6a tk1a tk2a tmra ti1a tk0a oka t1ab t2ab tadab tr1ab taq1 tala taw1 taw2 taw6 tamr tai1 tak0 tak1 tak2 iap0 iap1 iap2 iap3 iak tab1 tab2 tabad snzt1 snzt2 snzad snzcp rcp scp cmck crck dwdt adst wrst tam 0 tam 1 tam 2 tam 3 tam 4 tam 5 tam 6 tam 7 tam 8 tam 9 tam 10 tam 11 tam 12 tam 13 tam 14 tam 15 xam 0 xam 1 xam 2 xam 3 xam 4 xam 5 xam 6 xam 7 xam 8 xam 9 xam 10 xam 11 xam 12 xam 13 xam 14 xam 15 xami 0 xami 1 xami 2 xami 3 xami 4 xami 5 xami 6 xami 7 xami 8 xami 9 xami 10 xami 11 xami 12 xami 13 xami 14 xami 15 xamd 0 xamd 1 xamd 2 xamd 3 xamd 4 xamd 5 xamd 6 xamd 7 xamd 8 xamd 9 xamd 10 xamd 11 xamd 12 xamd 13 xamd 14 xamd 15 lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy tma 0 tma 1 tma 2 tma 3 tma 4 tma 5 tma 6 tma 7 tma 8 tma 9 tma 10 tma 11 tma 12 tma 13 tma 14 tma 15 bl bml bla bmla sea szd the second word 10 0aaa aaaa 10 0aaa aaaa 10 0p00 pppp 10 0p00 pppp 00 0111 nnnn 00 0010 1011 op0a op1a op2a op3a tpu0a tpu1a tpu2a d 3 d 0 hex. notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 a b c d e f d 9 d 4 20 100001 21 100010 22 100011 23 100100 24 100101 25 100110 26 100111 27 101000 28 101001 29 101010 2a 101011 2b 101100 2c 101101 2d 101110 2e 101111 2f 110000 111111 30 3f 100000 the above table shows the relationship between machine language codes and machine language instructions. d 3 d 0 show the low- order 4 bits of the machine language code, and d 9 d 4 show the high-order 6 bits of the machine language code. the hexadecimal representation of the code is also provided. there are one-word instructions and two-word instructions, but only the first word of each instruction is shown. do not use code marked . the codes for the second word of a two-word instruction are described below. instructions
1-104 rev.2.01 feb 02, 2005 4502 group hardware rej09b0193-0201 table 20 product of built-in prom version prom size ( ? ? built-in prom version in addition to the mask rom versions, the 4502 group has the one time prom versions whose proms can only be written to and not be erased. the built-in prom version has functions similar to those of the mask rom versions, but it has prom mode that enables writing to built-in prom. table 20 shows the product of built-in prom version. figure 56 shows the pin configurations of built-in prom versions. the one time prom version has pin-compatibility with the mask rom version. (1) prom mode the 4502 group has a prom mode in addition to a normal opera- tion mode. it has a function to serially input/output the command codes, addresses, and data required for operation (e.g., read and program) on the built-in prom using only a few pins. this mode can be selected by setting pins sda (serial data input/output), s clk (serial clock input), pgm to h after connecting wires as shown in figure 56 and powering on the v dd pin, and then apply- ing 12 v to the v pp pin. in the prom mode, three types of software commands (read, pro- gram, and program verify) can be used. clock-synchronous serial i/o is used, beginning from the lsb (lsb first). use the special-perpose serial programmer when performing serial read/program. as for the serial programmer for the single-chip microcomputer (se- rial programmer and control software), refer to the renesas microcomputer development support tools hompage ( http:// www.renesas.com/en/tools). fig. 55 flow of writing and test of the product shipped in blank rom type package part number (2) notes on handling ? ? note ) verify test with prom programmer f u n c t i o n t e s t i n t a r g e t d e v i c e since the screening temperature is highe r than storage temperature, never expose the microcomputer to 150 note: built-in prom version
1-105 4502 group hardware rev.2.01 feb 02, 2005 rej09b0193-0201 fig. 56 pin configuration of built-in prom version pin configuration (top view) v dd p 1 0 p 1 1 p1 2 /cntr p1 3 /int p 0 3 p 0 2 p 0 1 p0 0 v s s d 4 d 5 x i n x o u t c n v s s p2 1 /a in1 p2 0 /a in0 m 3 4 5 0 2 reset d 2 / c d 3 /k d 1 d 0 p 3 1 / a i n 3 p 3 0 / a i n 2 outline prsp0024ga-a (24p2q-a ) 1 7 1 8 2 1 2 0 2 2 1 9 2 3 2 4 1 6 1 5 1 4 1 3 8 7 4 5 3 6 2 1 9 10 11 12 v d d v s s v p p s clk s d a v dd p g m m 3 4 5 0 2 e 4 f p built-in prom version
chapter 2 application 2.1 i/o pins 2.2 interrupts 2.3 timers 2.4 a/d converter 2.5 reset 2.6 voltage drop detection circuit 2.7 ram back-up 2.8 oscillation circuit
2.1 i/o pins 2-2 rev.2.01 feb 02, 2005 4502 group application rej09b0193-0201 2.1 i/o pins the 4502 group has the eighteen i/o pins. (port p1 2 is also used as cntr i/o pin, port p1 3 is also used as int input pin, port p2 is also used as analog input pins a in0 and a in1 , port p3 is also used as analog input pins a in2 and a in3 , port d 2 is also used as port c, and port d 3 is also used as port k, respectively). this section describes each port i/o function, related registers, application example using each port function and notes. 2.1.1 i/o ports (1) port p0 port p0 is a 4-bit i/o port. port p0 has the key-on wakeup function which turns on/off with register k0 and pull-up transistor which turns on/off with register pu0. input/output of port p0 data input to port p0 set the output latch of specified port p0i (i=0 to 3) to ??with the op0a instruction. if the output latch is set to ?,???level is input. the state of port p0 is transferred to register a when the iap0 instruction is executed. data output from port p0 the contents of register a is output to port p0 with the op0a instruction. the output structure is an n-channel open-drain. (2) port p1 port p1 is a 4-bit i/o port. port p1 has the key-on wakeup function which turns on/off with register k1 and pull-up transistor which turns on/off with register pu1. input/output of port p1 data input to port p1 set the output latch of specified port p1i (i=0 to 3) to ??with the op1a instruction. if the output latch is set to ?,???level is input. the state of port p1 is transferred to register a when the iap1 instruction is executed. data output from port p1 the contents of register a is output to port p1 with the op1a instruction. the output structure is an n-channel open-drain. note: port p1 2 is also used as cntr. accordingly, when it is used as port p1 2 , set ??to the timer control register w6 0 .
2.1 i/o pins 2-3 4502 group application rev.2.01 feb 02, 2005 rej09b0193-0201 (3) port p2 port p2 is a 2-bit i/o port. also, its key-on wakeup function is switched to on/off by the register k2 0 and k2 1 , and its pull- up transistor function is switched to on/off by the register pu2 0 and pu2 1 . input/output of port p2 data input to port p2 set the output latch of specified port p2i (i=0, 1) to ??with the op2a instruction. if the output latch is set to ?,???level is input. the state of port p2 is transferred to register a when the iap2 instruction is executed. however, port p2 is 2 bits and a 2 and a 3 are fixed to ?. data output from port p2 the contents of register a is output to port p2 with the op2a instruction. the output structure is an n-channel open-drain. (4) port p3 port p3 is a 2-bit i/o port. input/output of port p3 data input to port p3 set the output latch of specified port p3i (i=0, 1) to ??with the op3a instruction. if the output latch is set to ?,???level is input. the state of port p3 is transferred to register a when the iap3 instruction is executed. however, port p3 is 2 bits and a 2 and a 3 are fixed to ?. data output from port p3 the contents of register a is output to port p3 with the op3a instruction. the output structure is an n-channel open-drain.
2.1 i/o pins 2-4 rev.2.01 feb 02, 2005 4502 group application rej09b0193-0201 (5) port d d 0 ? 5 are six independent i/o ports. also, as for ports d 2 and d 3 , its key-on wakeup function is switched to on/off by the register k2 2 and k2 3 , and its pull-up transistor function is switched to on/off by the register pu2 2 and pu2 3 . input/output of port d each pin of port d has an independent 1-bit wide i/o function. for i/o of ports d 0 ? 5 , select one of port d with the register y of the data pointer first. data input to port d set the output latch of specified port di (i = 0 to 5) to ??with the sd instruction. when the output latch is set to ?,???level is input. when the szd instruction is executed, if the port specified by register y is ?,?the next instruction is skipped. if it is ?,?the next instruction is executed. data output from port d set the output level to the output latch with the sd and rd instructions. the state of pin enters the high-impedance state when the sd instruction is executed. the states of all port d enter the high-impedance state when the cld instruction is executed. the state of pin becomes ??level when the rd instruction is executed. the output structure is an n-channel open-drain. notes 1: when the sd and rd instructions are used, do not set ?110 2 ?or more to register y. 2: port d 2 is also used as port c. accordingly, when using port d 2 , set the output latch to ??with the scp instruction. 3: port d 3 is also used as port k. accordingly, when using port d 3 , set the output latch to ??with the oka instruction.
2.1 i/o pins 2-5 4502 group application rev.2.01 feb 02, 2005 rej09b0193-0201 (6) port c port c is a 1-bit i/o port. input/output of port c data input to port c set the output latch of specified port c to ??with the scp instruction. if the output latch is set to ?,???level is input. when the snzcp instruction is executed, if the port c is ?,?the next instruction is skipped. if it is ?,?the next instruction is executed. data output from port c set the output level to the output latch with the scp and rcp instructions. the state of pin enters the high-impedance state when the scp instruction is executed. the state of pin becomes ??level when the rcp instruction is executed. the output structure is an n-channel open-drain. note: port c is also used as port d 2 . accordingly, when using port c, set the output latch to ??with the sd instruction. (7) port k port k is a 1-bit i/o port. input/output of port k data input to port k set the output latch of specified port k to ??with the oka instruction. if the output latch is set to ?,???level is input. the state of port k is transferred to register a when the iak instruction is executed. however, port k is 1 bit and a 1 , a 2 and a 3 are fixed to ?. data output from port k the contents of register a is output to port k with the oka instruction. the output structure is an n-channel open-drain. note: port k is also used as port d 3 . accordingly, when using port k, set the output latch to ??with the sd instruction.
2.1 i/o pins 2-6 rev.2.01 feb 02, 2005 4502 group application rej09b0193-0201 pull-up control register pu0 at reset : 0000 2 at ram back-up : state retained w pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on port p0 3 pull-up transistor control bit port p0 2 pull-up transistor control bit port p0 1 pull-up transistor control bit port p0 0 pull-up transistor control bit 0 1 0 1 0 1 0 1 pu0 3 pu0 2 pu0 1 pu0 0 note: ??represents write enabled. 2.1.2 related registers (1) key-on wakeup control register k0 register k0 controls the on/off of the key-on wakeup function of ports p0 0 ?0 3 . set the contents of this register through register a with the tk0a instruction. the contents of register k0 is transferred to register a with the tak0 instruction. table 2.1.1 shows the key-on wakeup control register k0. table 2.1.1 key-on wakeup control register k0 key-on wakeup control register k0 at reset : 0000 2 at ram back-up : state retained r/w key-on wakeup invalid key-on wakeup valid key-on wakeup invalid key-on wakeup valid key-on wakeup invalid key-on wakeup valid key-on wakeup invalid key-on wakeup valid port p0 3 key-on wakeup control bit port p0 2 key-on wakeup control bit port p0 1 key-on wakeup control bit port p0 0 key-on wakeup control bit 0 1 0 1 0 1 0 1 k0 3 k0 2 k0 1 k0 0 note: ??represents read enabled, and ??represents write enabled. (2) pull-up control register pu0 register pu0 controls the on/off of the ports p0 0 ?0 3 pull-up transistor. set the contents of this register through register a with the tpu0a instruction. table 2.1.2 shows the pull-up control register pu0. table 2.1.2 pull-up control register pu0
2.1 i/o pins 2-7 4502 group application rev.2.01 feb 02, 2005 rej09b0193-0201 pull-up control register pu1 at reset : 0000 2 at ram back-up : state retained w pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on port p1 3 /int pull-up transistor control bit port p1 2 /cntr pull-up transistor control bit port p1 1 pull-up transistor control bit port p1 0 pull-up transistor control bit 0 1 0 1 0 1 0 1 pu1 3 pu1 2 pu1 1 pu1 0 note: ??represents write enabled. (3) key-on wakeup control register k1 register k1 controls the on/off of the key-on wakeup function of ports p1 0 ?1 3 . set the contents of this register through register a with the tk1a instruction. the contents of register k1 is transferred to register a with the tak1 instruction. table 2.1.3 shows the key-on wakeup control register k1. table 2.1.3 key-on wakeup control register k1 key-on wakeup control register k1 at reset : 0000 2 at ram back-up : state retained r/w p1 3 key-on wakeup invalid/int pin key-on wakeup valid p1 3 key-on wakeup valid/int pin key-on wakeup invalid key-on wakeup invalid key-on wakeup valid key-on wakeup invalid key-on wakeup valid key-on wakeup invalid key-on wakeup valid port p1 3 /int key-on wakeup control bit port p1 2 /cntr key-on wakeup control bit port p1 1 key-on wakeup control bit port p1 0 key-on wakeup control bit 0 1 0 1 0 1 0 1 k1 3 k1 2 k1 1 k1 0 note: ??represents read enabled, and ??represents write enabled. (4) pull-up control register pu1 register pu1 controls the on/off of the ports p1 0 ?1 3 pull-up transistor. set the contents of this register through register a with the tpu1a instruction. table 2.1.4 shows the pull-up control register pu1. table 2.1.4 pull-up control register pu1
2.1 i/o pins 2-8 rev.2.01 feb 02, 2005 4502 group application rej09b0193-0201 pull-up control register pu2 at reset : 0000 2 at ram back-up : state retained w pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on port d 3 /k pull-up transistor control bit port d 2 /c pull-up transistor control bit port p2 1 /a in1 pull-up transistor control bit port p2 0 /a in0 pull-up transistor control bit 0 1 0 1 0 1 0 1 pu2 3 pu2 2 pu2 1 pu2 0 note: ??represents write enabled. (5) key-on wakeup control register k2 register k2 controls the on/off of the key-on wakeup function of ports p2 0 , p2 1 , d 2 /c and d 3 /k. set the contents of this register through register a with the tk2a instruction. the contents of register k2 is transferred to register a with the tak2 instruction. table 2.1.5 shows the key-on wakeup control register k2. table 2.1.5 key-on wakeup control register k2 key-on wakeup control register k2 at reset : 0000 2 at ram back-up : state retained r/w key-on wakeup invalid key-on wakeup valid key-on wakeup invalid key-on wakeup valid key-on wakeup invalid key-on wakeup valid key-on wakeup invalid key-on wakeup valid port d 3 /k key-on wakeup control bit port d 2 /c key-on wakeup control bit port p2 1 /a in1 key-on wakeup control bit port p2 0 /a in0 key-on wakeup control bit 0 1 0 1 0 1 0 1 k2 3 k2 2 k2 1 k2 0 note: ??represents read enabled, and ??represents write enabled. (6) pull-up control register pu2 register pu2 controls the on/off of the ports p2 0 , p2 1 , d 2 /c and d 3 /k pull-up transistor. set the contents of this register through register a with the tpu2a instruction. table 2.1.6 shows the pull-up control register pu2. table 2.1.6 pull-up control register pu2
2.1 i/o pins 2-9 4502 group application rev.2.01 feb 02, 2005 rej09b0193-0201 (7) timer control register w6 bit 0 of register w6 selects the p1 2 /cntr function, and bit 1 controls the cntr output. set the contents of this register through register a with the tw6a instruction. the contents of register w6 is transferred to register a with the taw6 instruction. table 2.1.7 shows the timer control register w6. table 2.1.7 timer control register w6 timer control register w6 at reset : 0000 2 at ram back-up : state retained r/w this bit has no function, but read/write is enabled. this bit has no function, but read/write is enabled. timer 1 underflow signal divided by 2 output timer 2 underflow signal divided by 2 output p1 2 (i/o) / cntr input p1 2 (input) / cntr input/output not used not used cntr output control bit p1 2 /cntr function selection bit 0 1 0 1 0 1 0 1 w6 3 w6 2 w6 1 w6 0 notes 1: ??represents read enabled, and ??represents write enabled. 2: when setting the port, w6 3 ?6 1 are not used.
2.1 i/o pins 2-10 rev.2.01 feb 02, 2005 4502 group application rej09b0193-0201 2.1.3 port application examples (1) key input by key scan key matrix can be set up by connecting keys externally because port d output structure is an n- channel open-drain and port p0 has the pull-up resistor. outline: the connecting required external part is just keys. specifications: port d is used to output ??level and port p0 is used to input 16 keys. figure 2.1.1 shows the key input and figure 2.1.2 shows the key input timing. fig. 2.1.1 key input by key scan sw4 sw3 sw2 sw8 sw7 s w 6 s w 9 sw11 sw10 s w 1 2 s w 1 6s w 1 5s w 1 4s w 1 3 d 0 d 1 d 2 d 3 p 0 0 p0 1 p 0 2 p 0 3 s w 1 s w 5 m 3 4 5 0 2 fig. 2.1.2 key scan input timing d 0 d 1 d 2 d 3 i a p 0iap0i a p 0iap0 i a p 0 h l h l h l h l i n p u t t o s w 1 s w 4 input to sw13 sw16 input to sw9 sw12 i n p u t t o s w 5 s w 8 i n p u t t o s w 1 s w 4 k e y i n p u t p e r i o d switching key input selection port (d d ) stabilizing wait time for input reading port (key input) n o t e : h o u t p u t o f p o r t d b e c o m e s h i g h - i m p e d a n c e s t a t e . 01
2.1 i/o pins 2-11 4502 group application rev.2.01 feb 02, 2005 rej09b0193-0201 2.1.4 notes on use (1) note when an i/o port is used as an input port set the output latch to 1 and input the port value before input. if the output latch is set to 0, l level can be input. (2) noise and latch-up prevention connect an approximate 0.1 f bypass capacitor directly to the v ss line and the v dd line with the thickest possible wire at the shortest distance, and equalize its wiring in width and length. the cnv ss pin is also used as the v pp pin (programming voltage = 12.5 v) at the one time prom version. connect the cnv ss /v pp pin to v ss through an approximate 5 k ? resistor which is connected to the cnv ss /v pp pin at the shortest distance. (3) note on multifunction the input/output of d 2 , d 3 , p1 2 and p1 3 can be used even when c, k, cntr (input) and int are selected. the input of p1 2 can be used even when cntr (output) is selected. the input/output of p2 0 , p2 1 , p3 0 and p3 1 can be used even when a in0 , a in1 , a in2 and a in3 are selected. (4) connection of unused pins table 2.1.8 shows the connections of unused pins. (5) sd, rd instructions when the sd and rd instructions are used, do not set 0110 2 or more to register y. (6) analog input pins when both analog input a in0 a in3 and i/o ports p2 and p3 function are used, note the following; selection of analog input pins even when p2 0 /a in0 , p2 1 /a in1 , p3 0 /a in2 , p3 1 /a in3 are set to pins for analog input, they continue to function as ports p2 and p3 input/output. accordingly, when any of them are used as i/o port and others are used as analog input pins, make sure to set the outputs of pins that are set for analog input to 1. also, the port input function of the pin functions as an analog input is undefined. (7) notes on port p1 3 /int pin when the bit 3 of register i1 is cleared, the ram back-up mode is selected and the input of int pin is disabled, be careful about the following notes. when the key-on wakeup function of port p1 3 is not used (register k1 3 = 0 ), clear bits 2 and 3 of register i1 before system enters to the ram back-up mode.
2.1 i/o pins 2-12 rev.2.01 feb 02, 2005 4502 group application rej09b0193-0201 table 2.1.6 connections of unused pins connection connect to v ss . open. open. (output latch is set to 1. ) open. (output latch is set to 0. ) connect to v ss . open. (output latch is set to 1. ) open. (output latch is set to 0. ) connect to v ss . open. (output latch is set to 1. ) open. (output latch is set to 0. ) connect to v ss . open. (output latch is set to 1. ) open. (output latch is set to 0. ) connect to v ss . open. (output latch is set to 1. ) open. (output latch is set to 0. ) connect to v ss . open. (output latch is set to 1. ) open. (output latch is set to 0. ) connect to v ss . open. (output latch is set to 1. ) open. (output latch is set to 0. ) connect to v ss . pin x in x out d 0 , d 1 d 4 , d 5 d 2 /c d 3 /k p0 0 p0 3 p1 0 , p1 1 p1 2 /cntr p1 3 /int p2 0 /a in0 p2 1 /a in1 p3 0 /a in2 p3 1 /a in3 usage condition system operates by the on-chip oscillator. ( note 1 ) system operates by the external clock. (the ceramic resonator is selected with the cmck instruction.) system operates by the rc oscillator. (the rc oscillation is selected with the crck instruction.) system operates by the on-chip oscillator. ( note 1 ) the key-on wakeup function is not selected. ( note 4 ) the pull-up function and the key-on wakeup function are not selected. ( notes 2, 3 ) the pull-up function and the key-on wakeup function are not selected. ( notes 2, 3 ) the key-on wakeup function is not selected. ( note 4 ) the pull-up function and the key-on wakeup function are not selected. ( notes 2, 3 ) the pull-up function and the key-on wakeup function are not selected. ( notes 2, 3 ) the key-on wakeup function is not selected. ( note 4 ) the pull-up function and the key-on wakeup function are not selected. ( notes 2, 3 ) the pull-up function and the key-on wakeup function are not selected. ( notes 2, 3 ) the key-on wakeup function is not selected. the input to int pin is disabled. ( notes 4, 5 ) the pull-up function and the key-on wakeup function are not selected. ( notes 2, 3 ) the pull-up function and the key-on wakeup function are not selected. ( notes 2, 3 ) the key-on wakeup function is not selected. ( note 4 ) the pull-up function and the key-on wakeup function are not selected. ( notes 2, 3 ) the pull-up function and the key-on wakeup function are not selected. ( notes 2, 3 ) notes 1: when the ceramic resonator or the rc oscillation is not selected by program, system operates by the on-chip oscillator (internal oscillator). 2: when the pull-up function is left valid, the supply current is increased. do not select the pull-up function. 3: when the key-on wakeup function is left valid, the system returns from the ram back-up state immediately after going into the ram back-up state. do not select the key-on wakeup function. 4: when selecting the key-on wakeup function, select also the pull-up function. 5: clear the bit 3 (i1 3 ) of register i1 to 0 to disable to input to int pin (after reset: i1 3 = 0 ) (note when connecting to v ss ) connect the unused pins to v ss using the thickest wire at the shortest distance against noise.
2.2 interrupts 2-13 4502 group application rev.2.01 feb 02, 2005 rej09b0193-0201 2.2 interrupts the 4502 group has four interrupt sources : external (int), timer 1, timer 2, and a/d. this section describes individual types of interrupts, related registers, application examples using interrupts and notes. 2.2.1 interrupt functions (1) external 0 interrupt (int) the interrupt request occurs by the change of input level of int pin. the interrupt valid waveform can be selected by the bits 1 and 2, and the int pin input is controlled by the bit 3 of the interrupt control register i1. external 0 interrupt int processing when the interrupt is used the interrupt occurrence is enabled when the bit 0 of the interrupt control register v1 and the interrupt enable flag inte are set to 1. when the external 0 interrupt occurs, the interrupt processing is executed from address 0 in page 1. when the interrupt is not used the interrupt is disabled and the snz0 instruction is valid when the bit 0 of register v1 is set to 0. (2) timer 1 interrupt the interrupt request occurs by the timer 1 underflow. timer 1 interrupt processing when the interrupt is used the interrupt occurrence is enabled when the bit 2 of the interrupt control register v1 and the interrupt enable flag inte are set to 1. when the timer 1 interrupt occurs, the interrupt processing is executed from address 4 in page 1. when the interrupt is not used the interrupt is disabled and the snzt1 instruction is valid when the bit 2 of register v1 is set to 0. (3) timer 2 interrupt the interrupt request occurs by the timer 2 underflow. timer 2 interrupt processing when the interrupt is used the interrupt occurrence is enabled when the bit 3 of the interrupt control register v1 and the interrupt enable flag inte are set to 1. when the timer 2 interrupt occurs, the interrupt processing is executed from address 6 in page 1. when the interrupt is not used the interrupt is disabled and the snzt2 instruction is valid when the bit 3 of register v1 is set to 0.
2.2 interrupts 2-14 rev.2.01 feb 02, 2005 4502 group application rej09b0193-0201 (4) a/d interrupt the interrupt request occurs by the end of the a/d conversion. a/d interrupt processing when the interrupt is used the interrupt occurrence is enabled when the bit 2 of the interrupt control register v2 and the interrupt enable flag inte are set to 1. when the a/d interrupt occurs, the interrupt processing is executed from address c in page 1. when the interrupt is not used the interrupt is disabled and the snzad instruction is valid when the bit 2 of register v2 is set to 0. 2.2.2 related registers (1) interrupt enable flag (inte) the interrupt enable flag (inte) controls whether the every interrupt enable/disable. interrupts are enabled when inte flag is set to 1 with the ei instruction and disabled when inte flag is cleared to 0 with the di instruction. when any interrupt occurs, the inte flag is automatically cleared to 0, so that other interrupts are disabled until the ei instruction is executed. note: the interrupt enabled with the ei instruction is performed after the ei instruction and one more instruction. (2) interrupt control register v1 interrupt enable bit of external 0, timer 1 and timer 2 are assigned to register v1. set the contents of this register through register a with the tv1a instruction. in addition, the tav1 instruction can be used to transfer the contents of register v1 to register a. table 2.2.1 shows the interrupt control register v1. table 2.2.1 interrupt control register v1 interrupt control register v1 at reset : 0000 2 at ram back-up : 0000 2 r/w interrupt disabled ( snzt2 instruction is valid) interrupt enabled ( snzt2 instruction is invalid) ( note 2 ) interrupt disabled ( snzt1 instruction is valid) interrupt enabled ( snzt1 instruction is invalid) ( note 2 ) this bit has no function, but read/write is enabled. interrupt disabled ( snz0 instruction is valid) interrupt enabled ( snz0 instruction is invalid) ( note 2 ) timer 2 interrupt enable bit timer 1 interrupt enable bit not used external 0 interrupt enable bit v1 3 v1 2 v1 1 v1 0 0 1 0 1 0 1 0 1 notes 1: r represents read enabled, and w represents write enabled. 2: these instructions are equivalent to the nop instruction. 3: when the interrupt is set, v1 1 is not used.
2.2 interrupts 2-15 4502 group application rev.2.01 feb 02, 2005 rej09b0193-0201 notes 1: r represents read enabled, and w represents write enabled. 2: this instruction is equivalent to the nop instruction. 3: when the interrupt is set, v2 3 , v2 1 and v2 0 are not used. (4) interrupt request flag the activated condition for each interrupt is examined. each interrupt request flag is set to 1 when the activated condition is satisfied, even if the interrupt is disabled by the inte flag or its interrupt enable bit. each interrupt request flag is cleared to 0 when either; an interrupt occurs, or the next instruction is skipped with a skip instruction. interrupt control register v2 at reset : 0000 2 at ram back-up : 0000 2 r/w this bit has no function, but read/write is enabled. interrupt disabled ( snzad instruction is valid) interrupt enabled ( snzad instruction is invalid) ( note 2 ) this bit has no function, but read/write is enabled. this bit has no function, but read/write is enabled. not used a/d interrupt enable bit not used not used v2 3 v2 2 v2 1 v2 0 0 1 0 1 0 1 0 1 (3) interrupt control register v2 interrupt enable bit of a/d is assigned to register v2. set the contents of this register through register a with the tv2a instruction. in addition, the tav2 instruction can be used to transfer the contents of register v2 to register a. table 2.2.2 shows the interrupt control register v2. table 2.2.2 interrupt control register v2
2.2 interrupts 2-16 rev.2.01 feb 02, 2005 4502 group application rej09b0193-0201 interrupt control register i1 at reset : 0000 2 at ram back-up : state retained r/w int pin input disabled int pin input enabled falling waveform ( l level of int pin is recognized with the snzi0 instruction)/ l level rising waveform ( h level of int pin is recognized with the snzi0 instruction)/ h level one-sided edge detected both edges detected disabled enabled int pin input control bit ( note 2 ) interrupt valid waveform for int pin/return level selection bit ( note 2 ) int pin edge detection circuit control bit int pin timer 1 control enable bit 0 1 0 1 0 1 0 1 i1 3 i1 2 i1 1 i1 0 notes 1: r represents read enabled, and w represents write enabled. 2: when the contents of i1 2 and i1 3 are changed, the external interrupt request flag exf0 may be set. accordingly, clear exf0 flag with the snz0 instruction when the bit 0 (v1 0 ) of register v1 to 0 . in this time, set the nop instruction after the snz0 instruction, for the case when a skip is performed with the snz0 instruction. (5) interrupt control register i1 the int pin timer 1 control enable bit is assigned to bit 0, int pin edge detection circuit control bit is assigned to bit 1, interrupt valid waveform for int pin/return level selection bit is assigned to bit 2 and int pin input control bit is assigned to bit 3. set the contents of this register through register a with the ti1a instruction. in addition, the tai1 instruction can be used to transfer the contents of register i1 to register a. table 2.2.3 shows the interrupt control register i1. table 2.2.3 interrupt control register i1
2.2 interrupts 2-17 4502 group application rev.2.01 feb 02, 2005 rej09b0193-0201 2.2.3 interrupt application examples (1) int interrupt the int pin is used for external 0 interrupt, of which valid waveforms can be chosen, which can recognize the change of both edges ( h l or l h ). outline: an external 0 interrupt can be used by dealing with the change of edge ( h l or l h ) in both directions as a trigger. specifications: an interrupt occurs by the change of an external signals edge ( h l or l h ). figure 2.2.1 shows an operation example of an external 0 interrupt, and figure 2.2.2 shows a setting example of an external 0 interrupt. (2) timer 1 interrupt constant period interrupts by a setting value to timer 1 can be used. outline: the constant period interrupts by the timer 1 underflow signal can be used. specifications: prescaler and timer 1 divide the system clock frequency f(x in ) = 4.0 mhz, and the timer 1 interrupt occurs every 1 ms. figure 2.2.3 shows a setting example of the timer 1 constant period interrupt. (3) timer 2 interrupt constant period interrupts by a setting value to timer 2 can be used. outline: the constant period interrupts by the timer 2 underflow signal can be used. specifications: timer 2 and prescaler divide the system clock frequency (= 4.0 mhz), and the timer 2 interrupt occurs every about 1 ms. figure 2.2.4 shows a setting example of the timer 2 constant period interrupt. fig. 2.2.1 int interrupt operation example p 1 3 / i n t p 1 3 / i n t h h l l an interrupt occurs after the valid waveform falling is detected. an interrupt occurs after the valid waveform rising is detected.
2.2 interrupts 2-18 rev.2.01 feb 02, 2005 4502 group application rej09b0193-0201 fig. 2.2.2 int interrupt setting example note: the valid waveforms causing the interrupt must be retained at their level for 4 cycles or more of system clock. ? s e t p o r t p o r t u s e d f o r i n t i n t e r r u p t i s s e t t o i n p u t p o r t . 0 b 3b 0 b 3b 0 1 ?? both edges detection selected ( ti1a instruction) b 3b 0 1 1 b 3b 0 ? d i s a b l e i n t e r r u p t s i n t i n t e r r u p t i s t e m p o r a r i l y d i s a b l e d . i n t e r r u p t e n a b l e f l a g i n t e i n t e r r u p t c o n t r o l r e g i s t e r v 1 i n t e r r u p t c o n t r o l r e g i s t e r v 1 i n t e r r u p t e n a b l e f l a g i n t e 0 ??? a l l i n t e r r u p t s d i s a b l e d ( d i i n s t r u c t i o n ) i n t i n t e r r u p t o c c u r r e n c e d i s a b l e d ( t v 1 a i n s t r u c t i o n ) p o r t p 1 3 o u t p u t l a t c h ? ?? s e t t o i n p u t ( o p 1 a i n s t r u c t i o n ) ? s e t v a l i d w a v e f o r m v a l i d w a v e f o r m o f i n t p i n i s s e l e c t e d . b o t h e d g e s d e t e c t i o n s e l e c t e d i n t e r r u p t c o n t r o l r e g i s t e r i 1 ? c l e a r i n t e r r u p t r e q u e s t i n t i n t e r r u p t a c t i v a t e d c o n d i t i o n i s c l e a r e d . i n t i n t e r r u p t r e q u e s t f l a g e x f 0 0 i n t i n t e r r u p t a c t i v a t e d c o n d i t i o n c l e a r e d ( s n z 0 i n s t r u c t i o n ) note when the interrupt request is cleared when ? is executed, considering the skip of the next instruction according to the interrupt request flag exf0, insert the nop instruction after the snz0 instruction. ? e n a b l e i n t e r r u p t s t h e i n t i n t e r r u p t w h i c h i s t e m p o r a r i l y d i s a b l e d i s e n a b l e d . 1 ??? int interrupt occurrence enabled ( tv1a instruction) all interrupts enabled ( ei instruction) i n t i n t e r r u p t e x e c u t i o n s t a r t e d ? : i t c a n b e 0 o r 1 . 1 ? e x e c u t e n o p i n s t r u c t i o n n o p i n s t r u c t i o n
2.2 interrupts 2-19 4502 group application rev.2.01 feb 02, 2005 rej09b0193-0201 fig. 2.2.3 timer 1 constant period interrupt setting example b 3b 0 0 1 b 3b 0 1 b 3b 0 1 11 0 0 b 3b 0 ? d i s a b l e i n t e r r u p t s t i m e r 1 i n t e r r u p t i s t e m p o r a r i l y d i s a b l e d . i n t e r r u p t e n a b l e f l a g i n t e i n t e r r u p t c o n t r o l r e g i s t e r v 1 0 ??? a l l i n t e r r u p t s d i s a b l e d ( d i i n s t r u c t i o n ) t i m e r 1 i n t e r r u p t o c c u r r e n c e d i s a b l e d ( t v 1 a i n s t r u c t i o n ) ? s t o p t i m e r o p e r a t i o n t i m e r 1 a n d p r e s c a l e r a r e t e m p o r a r i l y s t o p p e d . d i v i d i n g r a t i o o f p r e s c a l e r i s s e l e c t e d . t i m e r c o n t r o l r e g i s t e r w 1 t i m e r 1 s t o p ( t w 1 a i n s t r u c t i o n ) p r e s c a l e r s t o p p r e s c a l e r d i v i d e d b y 1 6 s e l e c t e d ? s e t t i m e r v a l u e t i m e r 1 c o u n t t i m e i s s e t . ( t h e f o r m u l a i s s h o w n ? a b e l o w . ) t i m e r 1 r e l o a d r e g i s t e r r 1 5 2 1 6 t i m e r c o u n t v a l u e 8 2 s e t ( t 1 a b i n s t r u c t i o n ) ? c l e a r i n t e r r u p t r e q u e s t t i m e r 1 i n t e r r u p t a c t i v a t e d c o n d i t i o n i s c l e a r e d . t i m e r 1 i n t e r r u p t r e q u e s t f l a g t 1 f 0 t i m e r 1 i n t e r r u p t a c t i v a t e d c o n d i t i o n c l e a r e d ( s n z t 1 i n s t r u c t i o n ) n o t e w h e n t h e i n t e r r u p t r e q u e s t i s c l e a r e d w h e n ? i s e x e c u t e d , c o n s i d e r i n g t h e s k i p o f t h e n e x t i n s t r u c t i o n a c c o r d i n g t o t h e i n t e r r u p t r e q u e s t f l a g t 1 f , i n s e r t t h e n o p i n s t r u c t i o n a f t e r t h e s n z t 1 i n s t r u c t i o n . ? s t a r t t i m e r o p e r a t i o n t i m e r 1 a n d p r e s c a l e r t e m p o r a r i l y s t o p p e d a r e r e s t a r t e d . t i m e r c o n t r o l r e g i s t e r w 1 t i m e r 1 o p e r a t i o n s t a r t ( t w 1 a i n s t r u c t i o n ) p r e s c a l e r o p e r a t i o n s t a r t ? e n a b l e i n t e r r u p t s t h e t i m e r 1 i n t e r r u p t w h i c h i s t e m p o r a r i l y d i s a b l e d i s e n a b l e d . i n t e r r u p t c o n t r o l r e g i s t e r v 1 i n t e r r u p t e n a b l e f l a g i n t e 1 t i m e r 1 i n t e r r u p t o c c u r r e n c e e n a b l e d ( t v 1 a i n s t r u c t i o n ) a l l i n t e r r u p t s e n a b l e d ( e i i n s t r u c t i o n ) ??? c o n s t a n t p e r i o d i n t e r r u p t e x e c u t i o n s t a r t ? a t h e p r e s c a l e r d i v i d i n g r a t i o a n d t i m e r 1 c o u n t v a l u e t o m a k e t h e i n t e r r u p t o c c u r e v e r y 1 m s a r e s e t a s f o l l o w s . 1 m s ? ( 4 . 0 m h z ) ? 3 ? 1 6 ? ( 8 2 + 1 ) 1 s y s t e m c l o c k i n s t r u c t i o n c l o c k p r e s c a l e r d i v i d i n g r a t i o t i m e r 1 c o u n t v a l u e ? : i t c a n b e 0 o r 1 . 0 0
2.2 interrupts 2-20 rev.2.01 feb 02, 2005 4502 group application rej09b0193-0201 fig. 2.2.4 timer 2 constant period interrupt setting example 0 b3 b 0 ? d i s a b l e i n t e r r u p t s t i m e r 2 i n t e r r u p t i s t e m p o r a r i l y d i s a b l e d . interrupt enable flag inte i n t e r r u p t c o n t r o l r e g i s t e r v 1 0 ??? all interrupts disabled ( di instruction) t i m e r 2 i n t e r r u p t o c c u r r e n c e d i s a b l e d ( t v 1 a i n s t r u c t i o n ) b3 b 0 0 1 ? s t o p t i m e r 2 o p e r a t i o n t i m e r 2 a n d p r e s c a l e r a r e t e m p o r a r i l y s t o p p e d . d i v i d i n g r a t i o o f p r e s c a l e r i s s e l e c t e d . t i m e r c o n t r o l r e g i s t e r w 1 p r e s c a l e r s t o p ( t w 1 a i n s t r u c t i o n ) p r e s c a l e r d i v i d e d b y 1 6 s e l e c t e d f o r c o u n t s o u r c e ? s e t t i m e r v a l u e t i m e r 2 c o u n t t i m e i s s e t . ( t h e f o r m u l a i s s h o w n ? a b e l o w . ) t i m e r 2 r e l o a d r e g i s t e r r 2 52 16 t i m e r c o u n t v a l u e 8 2 s e t ( t 2 a b i n s t r u c t i o n ) ? clear interrupt request timer 2 interrupt activated condition is cleared. t i m e r 2 i n t e r r u p t r e q u e s t f l a g t 2 f 0 timer 2 interrupt activated condition cleared ( snzt2 instruction) n o t e w h e n t h e i n t e r r u p t r e q u e s t i s c l e a r e d w h e n ? i s e x e c u t e d , c o n s i d e r i n g t h e s k i p o f t h e n e x t i n s t r u c t i o n a c c o r d i n g t o t h e i n t e r r u p t r e q u e s t f l a g t 2 f , i n s e r t t h e n o p i n s t r u c t i o n a f t e r t h e s n z t 2 i n s t r u c t i o n . b3 b0 ? 1 ? ? s t a r t t i m e r 2 o p e r a t i o n t i m e r 2 a n d p r e s c a l e r t e m p o r a r i l y s t o p p e d a r e r e s t a r t e d . t i m e r c o n t r o l r e g i s t e r w 1 prescaler operation start ( tw1a instruction) 1 b 3b0 1 ? e n a b l e i n t e r r u p t s t h e t i m e r 2 i n t e r r u p t w h i c h i s t e m p o r a r i l y d i s a b l e d i s e n a b l e d . i n t e r r u p t c o n t r o l r e g i s t e r v 1 1 timer 2 interrupt occurrence enabled ( tv1a instruction) all interrupts enabled ( ei instruction) ??? c o n s t a n t p e r i o d i n t e r r u p t e x e c u t i o n s t a r t ? a the prescaler dividing ratio and timer 2 count value to make the interrupt occur every about 1 ms are set as follows. 1 m s ? ( 4 . 0 m h z ) ? 3 ? 1 6 ? ( 8 2 + 1 ) 1 system cloc k instruction clock prescaler dividing ratio timer 2count value ? : i t c a n b e 0 o r 1 . b3 b 0 0 1 0 t i m e r c o n t r o l r e g i s t e r w 2 ? t i m e r 2 s t o p ( t w 2 a i n s t r u c t i o n ) p r e s c a l e r o u t p u t s e l e c t e d f o r c o u n t s o u r c e ?? b 3b0 0 11 t i m e r c o n t r o l r e g i s t e r w 2t i m e r 2 o p e r a t i o n s t a r t ( t w 2 a i n s t r u c t i o n ) ? interrupt enable flag inte
2.2 interrupts 2-21 4502 group application rev.2.01 feb 02, 2005 rej09b0193-0201 2.2.4 notes on use (1) setting of int interrupt valid waveform set a value to the bit 2 of register i1, and execute the snz0 instruction to clear the exf0 flag to 0 after executing at least one instruction. depending on the input state of p1 3 /int pin, the external interrupt request flag (exf0) may be set to 1 when the interrupt valid waveform is changed. (2) setting of int pin input control set a value to the bit 3 of register i1, and execute the snz0 instruction to clear the exf0 flag to 0 after executing at least one instruction. depending on the input state of p1 3 /int pin, the external interrupt request flag (exf0) may be set to 1 when the interrupt valid waveform is changed. (3) multiple interrupts multiple interrupts cannot be used in the 4502 group. (4) notes on interrupt processing when the interrupt occurs, at the same time, the interrupt enable flag inte is cleared to 0 (interrupt disable state). in order to enable the interrupt at the same time when system returns from the interrupt, write ei and rti instructions continuously. (5) p1 3 /int pin the p1 3 /int pin need not be selected the external interrupt input int function or the normal output port p1 3 function. however, the exf0 flag is set to 1 when a valid waveform is input to int pin even if it is used as an i/o port p1 3 . (6) power down instruction be sure to disable interrupts by executing the di instruction before executing the epof instruction.
2.3 timers 2-22 rev.2.01 feb 02, 2005 4502 group application rej09b0193-0201 2.3 timers the 4502 group has two 8-bit timers (each has a reload register) and a 16-bit fixed dividing frequency timer which has the watchdog timer function. this section describes individual types of timers, related registers, application examples using timers and notes. 2.3.1 timer functions (1) timer 1 timer operation (timer 1 has the timer 1 count start trigger function from p1 3 /int pin input) (2) timer 2 timer operation (3) 16-bit timer watchdog function watchdog timer provides a method to reset the system when a program run-away occurs. system operates after it is released from reset. when the timer count value underflows, the wdf1 flag is set to 1. then, if the wrst instruction is never executed until timer wdt counts 65534, wdf2 flag is set to 1, and system reset occurs. when the dwdt instruction and the wrst instruction are executed continuously, the watchdog timer function is invalid. the wrst instruction has the skip function. when the wrst instruction is executed while the wdf1 flag is 1 , the wdf1 flag is cleared to 0 and the next instruction is skipped.
2.3 timers 2-23 4502 group application rev.2.01 feb 02, 2005 rej09b0193-0201 2.3.2 related registers (1) interrupt control register v1 the external 0 interrupt enable bit is assigned to bit 0, timer 1 interrupt enable bit is assigned to bit 2, and the timer 2 interrupt enable bit is assigned to bit 3. set the contents of this register through register a with the tv1a instruction. the tav1 instruction can be used to transfer the contents of register v1 to register a. table 2.3.1 shows the interrupt control register v1. table 2.3.1 interrupt control register v1 interrupt control register v1 at reset : 0000 2 at ram back-up : 0000 2 r/w interrupt disabled ( snzt2 instruction is valid) interrupt enabled ( snzt2 instruction is invalid) ( note 2 ) interrupt disabled ( snzt1 instruction is valid) interrupt enabled ( snzt1 instruction is invalid) ( note 2 ) this bit has no function, but read/write is enabled. interrupt disabled ( snz0 instruction is valid) interrupt enabled ( snz0 instruction is invalid) ( note 2 ) timer 2 interrupt enable bit timer 1 interrupt enable bit not used external 0 interrupt enable bit v1 3 v1 2 v1 1 v1 0 0 1 0 1 0 1 0 1 notes 1: r represents read enabled, and w represents write enabled. 2: these instructions are equivalent to the nop instruction. 3: when timer is used, v1 1 and v1 0 are not used. (2) timer control register w1 the timer 1 count start synchronous circuit control bit is assigned to bit 0, the timer 1 control bit is assigned to bit 1, the prescaler dividing ratio selection bit is assigned to bit 2, and the prescaler control bit is assigned to bit 3. set the contents of this register through register a with the tw1a instruction. the taw1 instruction can be used to transfer the contents of register w1 to register a. table 2.3.2 shows the timer control register w1. table 2.3.2 timer control register w1 timer control register w1 at reset : 0000 2 at ram back-up : 0000 2 r/w stop (state initialized) operating instruction clock divided by 4 instruction clock divided by 16 stop (state retained) operating count start synchronous circuit not selected count start synchronous circuit selected prescaler control bit prescaler dividing ratio selection bit timer 1 control bit timer 1 count start synchronous circuit control bit w1 3 w1 2 w1 1 w1 0 0 1 0 1 0 1 0 1 note: r represents read enabled, and w represents write enabled.
2.3 timers 2-24 rev.2.01 feb 02, 2005 4502 group application rej09b0193-0201 (3) timer control register w2 the timer 2 count source selection bits are assigned to bits 0 and 1, the timer 1 count auto-stop circuit control bit is assigned to bit 2 and the timer 2 control bit is assigned to bit 3. set the contents of this register through register a with the tw2a instruction. the taw2 instruction can be used to transfer the contents of register w2 to register a. table 2.3.3 shows the timer control register w2. table 2.3.3 timer control register w2 timer control register w2 at reset : 0000 2 at ram back-up : state retained r/w stop (state retained) operating count auto-stop circuit not selected count auto-stop circuit selected count source timer 1 underflow signal prescaler output (orclk) cntr input system clock timer 2 control bit timer 1 count auto-stop circuit control bit ( note 2 ) timer 2 count source selection bits w2 3 w2 2 w2 1 w2 0 0 1 0 1 notes 1: r represents read enabled, and w represents write enabled. 2: this function is valid only when the timer 1 count start synchronous circuit is selected. (4) timer control register w6 the p1 2 /cntr function selection bit is assigned to bit 0 and the cntr output control bit is assigned to bit 1. set the contents of this register through register a with the tw6a instruction. the taw6 instruction can be used to transfer the contents of register w6 to register a. table 2.3.4 shows the timer control register w6. table 2.3.4 timer control register w6 w2 1 0 0 1 1 w2 0 0 1 0 1 timer control register w6 at reset : 0000 2 at ram back-up : state retained r/w this bit has no function, but read/write is enabled. this bit has no function, but read/write is enabled. timer 1 underflow signal divided by 2 output timer 2 underflow signal divided by 2 output p1 2 (i/o) / cntr input ( note 2 ) p1 2 (input) / cntr i/o ( note 2 ) not used not used cntr output control bit p1 2 /cntr function selection bit w6 3 w6 2 w6 1 w6 0 0 1 0 1 0 1 0 1 notes 1: r represents read enabled, and w represents write enabled. 2: the cntr input is valid only when the cntr input is selected for the timer 2 count source. 3: when timer is used, w6 3 and w6 2 are not used.
2.3 timers 2-25 4502 group application rev.2.01 feb 02, 2005 rej09b0193-0201 2.3.3 timer application examples (1) timer operation: measurement of constant period the constant period by the setting timer count value can be measured. outline: the constant period by the timer 1 underflow signal can be measured. specifications: timer 1 and prescaler divides the system clock frequency f(x in ) = 4.0 mhz, and the timer 1 interrupt request occurs every 3 ms. figure 2.3.3 shows the setting example of the constant period measurement. (2) cntr output operation: piezoelectric buzzer output outline: square wave output from timer 1 can be used for piezoelectric buzzer output. specifications: 4 khz square wave is output from the cntr pin at system clock frequency f(x in ) = 4.0 mhz. also, timer 1 interrupt occurs simultaneously. figure 2.3.1 shows the peripheral circuit example, and figure 2.3.4 shows the setting example of cntr output. fig. 2.3.1 peripheral circuit example (3) cntr input operation: event count outline: count operation can be performed by using the signal (falling waveform) input from cntr pin as the event. specifications: the low-frequency pulse from external as the timer 2 count source is input to cntr pin, and the timer 2 interrupt request occurs every 100 counts. figure 2.3.5 shows the setting example of cntr input. 4502 cntr 1 2 5 s1 2 5 s set dividing ratio for timer 1 underflow cycle to 125 s. in order to reduce the current dissipation, output is high-impedance state during buzzer output stop.
2.3 timers 2-26 rev.2.01 feb 02, 2005 4502 group application rej09b0193-0201 (4) timer operation: timer start by external input outline: the constant period can be measured by external input. specifications: system clock frequency f(x in ) = 4 mhz and timer 1 operates by int input as a trigger and an interrupt occurs after 1 ms. figure 2.3.6 shows the setting example of timer start. (5) watchdog timer watchdog timer provides a method to reset the system when a program run-away occurs. accordingly, when the watchdog timer function is set to be valid, execute the wrst instruction at a certain period which consists of timer 16-bit timers 65534 counts or less (execute wrst instruction at a cycle of 65534 machine cycles or less). outline: execute the wrst instruction in 16-bit timer s 65534 counts at the normal operation. if a program runs incorrectly, the wrst instruction is not executed and system reset occurs. specifications: system clock frequency f(x in ) = 4.0 mhz is used, and program run-away is detected by executing the wrst instruction in 49 ms. figure 2.3.2 shows the watchdog timer function, and figure 2.3.7 shows the example of watchdog timer. fig. 2.3.2 watchdog timer function 6 5 5 3 4 c o u n t ( n o t e ) v a l u e o f 1 6 - b i t t i m e r ( w d t ) wdf1 flag ? wrst instruction executed (skip executed) reset pin output w d f 2 f l a g ? s y s t e m r e s e t ? r e s e t r e l e a s e d ? a f t e r s y s t e m i s r e l e a s e d f r o m r e s e t ( = a f t e r p r o g r a m i s s t a r t e d ) , t i m e r w d t s t a r t s c o u n t d o w n . ? w h e n t i m e r w d t u n d e r f l o w o c c u r s , w d f 1 f l a g i s s e t t o 1 . ? w h e n t h e w r s t i n s t r u c t i o n i s e x e c u t e d , w d f 1 f l a g i s c l e a r e d t o 0 , t h e n e x t i n s t r u c t i o n i s s k i p p e d . ? w h e n t i m e r w d t u n d e r f l o w o c c u r s w h i l e w d f 1 f l a g i s 1 , w d f 2 f l a g i s s e t t o 1 a n d t h e w a t c h d o g r e s e t s i g n a l i s o u t p u t . ? t h e o u t p u t t r a n s i s t o r o f r e s e t p i n i s t u r n e d o n b y t h e w a t c h d o g r e s e t s i g n a l a n d s y s t e m r e s e t i s e x e c u t e d . n o t e : t h e n u m b e r o f c o u n t i s e q u a l t o t h e n u m b e r o f m a c h i n e c y c l e b e c a u s e t h e c o u n t s o u r c e o f w a t c h d o g t i m e r i s t h e i n s t r u c t i o n c l o c k . ffff 16 0000 16 ? ? ?
2.3 timers 2-27 4502 group application rev.2.01 feb 02, 2005 rej09b0193-0201 fig. 2.3.3 constant period measurement setting example 0 b3 b 0 ? d i s a b l e i n t e r r u p t s t i m e r 1 i n t e r r u p t i s t e m p o r a r i l y d i s a b l e d . i n t e r r u p t e n a b l e f l a g i n t e i n t e r r u p t c o n t r o l r e g i s t e r v 1 0 ?? ? all interrupts disabled ( di instruction) timer 1 interrupt occurrence disabled ( tv1a instruction) b 3b0 0 1 ? s t o p t i m e r o p e r a t i o n t i m e r 1 a n d p r e s c a l e r a r e t e m p o r a r i l y s t o p p e d . d i v i d i n g r a t i o o f p r e s c a l e r i s s e l e c t e d . t i m e r c o n t r o l r e g i s t e r w 1 0 t i m e r 1 s t o p ( t w 1 a i n s t r u c t i o n ) p r e s c a l e r s t o p p r e s c a l e r d i v i d e d b y 1 6 s e l e c t e d 0 ? s e t t i m e r v a l u e t i m e r 1 c o u n t t i m e i s s e t . ( t h e f o r m u l a i s s h o w n ? a b e l o w . ) timer 1 reload register r1 f 9 1 6 timer count value 249 set ( t1ab instruction) ? c l e a r i n t e r r u p t r e q u e s t t i m e r 1 i n t e r r u p t a c t i v a t e d c o n d i t i o n i s c l e a r e d . timer 1 interrupt request flag t1f 0 timer 1 interrupt activated condition cleared ( snzt1 instruction) n o t e w h e n t h e i n t e r r u p t r e q u e s t i s c l e a r e d w h e n ? i s e x e c u t e d , c o n s i d e r i n g t h e s k i p o f t h e n e x t i n s t r u c t i o n a c c o r d i n g t o t h e i n t e r r u p t r e q u e s t f l a g t 1 f , i n s e r t t h e n o p i n s t r u c t i o n a f t e r t h e s n z t 1 i n s t r u c t i o n . ? s t a r t t i m e r 1 o p e r a t i o n t i m e r 1 a n d p r e s c a l e r t e m p o r a r i l y s t o p p e d a r e r e s t a r t e d . t i m e r 1 o p e r a t i o n s t a r t ( t w 1 a i n s t r u c t i o n ) p r e s c a l e r o p e r a t i o n s t a r t b 3b0 11 t i m e r c o n t r o l r e g i s t e r w 1 0 1 b 3b 0 1 ? enable interrupts the timer 1 interrupt which is temporarily disabled is enabled. interrupt control register v1 1 timer 1 interrupt occurrence enabled ( tv1a instruction) all interrupts enabled ( ei instruction) ?? ? c o n s t a n t p e r i o d i n t e r r u p t e x e c u t i o n s t a r t ? a t h e p r e s c a l e r d i v i d i n g r a t i o a n d t i m e r 1 c o u n t v a l u e t o m a k e t h e i n t e r r u p t o c c u r e v e r y 3 m s a r e s e t a s f o l l o w s . 3 m s = ( 4 . 0 m h z ) ? 3 ? 1 6 ? ( 2 4 9 + 1 ) 1 s y s t e m c l o c k instruction clock prescaler dividing ratio t i m e r 1 c o u n t v a l u e ? : i t c a n b e 0 o r 1 . interrupt enable flag inte
2.3 timers 2-28 rev.2.01 feb 02, 2005 4502 group application rej09b0193-0201 fig. 2.3.4 cntr output setting example 0 b 3b0 ? d i s a b l e i n t e r r u p t s t i m e r 1 i n t e r r u p t i s t e m p o r a r i l y d i s a b l e d . i n t e r r u p t e n a b l e f l a g i n t e i n t e r r u p t c o n t r o l r e g i s t e r v 1 0 ?? ? a l l i n t e r r u p t s d i s a b l e d ( d i i n s t r u c t i o n ) t i m e r 1 i n t e r r u p t o c c u r r e n c e d i s a b l e d ( t v 1 a i n s t r u c t i o n ) b 3b 0 0 0 ? s t o p t i m e r o p e r a t i o n t i m e r 1 a n d p r e s c a l e r a r e t e m p o r a r i l y s t o p p e d . d i v i d i n g r a t i o o f p r e s c a l e r i s s e l e c t e d . t i m e r c o n t r o l r e g i s t e r w 1 t i m e r 1 s t o p ( t w 1 a i n s t r u c t i o n ) p r e s c a l e r s t o p p r e s c a l e r d i v i d e d b y 4 s e l e c t e d 0 ? s e t t i m e r v a l u e , s e l e c t c n t r o u t p u t c n t r o u t p u t i s s e l e c t e d . t i m e r 1 c o u n t t i m e i s s e t . t i m e r c o n t r o l r e g i s t e r w 6 t i m e r 1 r e l o a d r e g i s t e r r 1 29 16 timer count value 41 set ( t1ab instruction) b 3b0 1 ? 0 cntr output selected ( tw6a instruction) ? c l e a r i n t e r r u p t r e q u e s t t i m e r 1 i n t e r r u p t a c t i v a t e d c o n d i t i o n i s c l e a r e d . timer 1 interrupt request flag t1f 0 timer 1 interrupt activated condition cleared ( snzt1 instruction) n o t e w h e n t h e i n t e r r u p t r e q u e s t i s c l e a r e d w h e n ? i s e x e c u t e d , c o n s i d e r i n g t h e s k i p o f t h e n e x t i n s t r u c t i o n a c c o r d i n g t o t h e i n t e r r u p t r e q u e s t f l a g t 1 f , i n s e r t t h e n o p i n s t r u c t i o n a f t e r t h e s n z t 1 i n s t r u c t i o n . ? start timer 1 operation timer 1 and prescaler temporarily stopped are restarted. timer 1 operation start ( tw1a instruction) prescaler operation start b 3b 0 1 0 t i m e r c o n t r o l r e g i s t e r w 1 0 1 b3 b0 1 ? e n a b l e i n t e r r u p t s t h e t i m e r 1 i n t e r r u p t w h i c h i s t e m p o r a r i l y d i s a b l e d i s e n a b l e d . i n t e r r u p t c o n t r o l r e g i s t e r v 1 1 t i m e r 1 i n t e r r u p t o c c u r r e n c e e n a b l e d ( t v 1 a i n s t r u c t i o n ) a l l i n t e r r u p t s e n a b l e d ( e i i n s t r u c t i o n ) ?? ? b 3b0 0 ? stop cntr output p1 2 /cntr i/o port is set to cntr input port, and it is set to the high-impedance state. t i m e r c o n t r o l r e g i s t e r w 6 c n t r i n p u t p i n s e t ( t w 6 a i n s t r u c t i o n ) ?? 0 ? : it can be 0 or 1. 0 interrupt enable flag inte i n p u t m o d e i s s e t . ( o p 1 a i n s t r u c t i o n ) output latch of port p1 2 b 3b0 ?? 1 ?
2.3 timers 2-29 4502 group application rev.2.01 feb 02, 2005 rej09b0193-0201 fig. 2.3.5 cntr input setting example however, specify the pulse width input to cntr pin. refer to section 2.3.4 notes on use for the timer external input period condition. 0 b3 b0 ? d i s a b l e i n t e r r u p t s t i m e r 2 i n t e r r u p t i s t e m p o r a r i l y d i s a b l e d . i n t e r r u p t e n a b l e f l a g i n t e interrupt control register v1 0 ?? ? all interrupts disabled ( di instruction) timer 2 interrupt occurrence disabled ( tv1a instruction) b3 b0 0 0 ? s t o p t i m e r o p e r a t i o n t i m e r o p e r a t i o n i s t e m p o r a r i l y s t o p p e d . t i m e r 2 c o u n t s o u r c e i s s e l e c t e d . t i m e r c o n t r o l r e g i s t e r w 2 ? t i m e r 2 s t o p ( t w 2 a i n s t r u c t i o n ) c n t r i n p u t s e l e c t e d f o r c o u n t s o u r c e 1 ? s e t t i m e r v a l u e t i m e r 2 c o u n t t i m e i s s e t . t i m e r 2 r e l o a d r e g i s t e r r 2 6 3 1 6 t i m e r c o u n t v a l u e 9 9 s e t ( t 2 a b i n s t r u c t i o n ) note when the interrupt request is cleared when ? is executed, considering the skip of the next instruction according to the interrupt request flag t2f, insert the nop instruction after the snzt2 instruction. ? s t a r t t i m e r 2 o p e r a t i o n t i m e r 2 t e m p o r a r i l y s t o p p e d i s r e s t a r t e d . t i m e r 2 o p e r a t i o n s t a r t ( t w 2 a i n s t r u c t i o n ) b 3b 0 1 0 t i m e r c o n t r o l r e g i s t e r w 2 ? 1 b3 b 0 1 ? enable interrupts the timer 2 interrupt which is temporarily disabled is enabled. interrupt control register v1 1 t i m e r 2 i n t e r r u p t o c c u r r e n c e e n a b l e d ( t v 1 a i n s t r u c t i o n ) a l l i n t e r r u p t s e n a b l e d ( e i i n s t r u c t i o n ) ?? ? ? : i t c a n b e 0 o r 1 . i n t e r r u p t e n a b l e f l a g i n t e ? c l e a r i n t e r r u p t r e q u e s t t i m e r 2 i n t e r r u p t a c t i v a t e d c o n d i t i o n i s c l e a r e d . timer 2 interrupt request flag t2f 0 timer 2 interrupt activated condition cleared ( snzt2 instruction) ? s e t p o r t p 1 2 p 1 2 /c n t r i / o p o r t i s s e t t o i n p u t p o r t . b3 b0 ? timer control register w6 port p1 2 (i/o) set ( tw6a instruction) ?? 0 input mode is set. ( op1a instruction) o u t p u t l a t c h o f p o r t p 1 2 b 3b0 ?? 1 ?
2.3 timers 2-30 rev.2.01 feb 02, 2005 4502 group application rej09b0193-0201 fig. 2.3.6 timer start by external input setting example (1) 0 b 3b0 ? d i s a b l e i n t e r r u p t s t i m e r 1 i n t e r r u p t a n d i n t i n t e r r u p t a r e t e m p o r a r i l y d i s a b l e d . i n t e r r u p t e n a b l e f l a g i n t e i n t e r r u p t c o n t r o l r e g i s t e r v 1 0 ?? a l l i n t e r r u p t s d i s a b l e d ( d i i n s t r u c t i o n ) t i m e r 1 i n t e r r u p t o c c u r r e n c e d i s a b l e d ( t v 1 a i n s t r u c t i o n ) i n t i n t e r r u p t o c c u r r e n c e d i s a b l e d 0 b3 b0 0 1 ? s t o p t i m e r o p e r a t i o n t i m e r 1 a n d p r e s c a l e r a r e t e m p o r a r i l y s t o p p e d . d i v i d i n g r a t i o o f p r e s c a l e r i s s e l e c t e d . t i m e r c o n t r o l r e g i s t e r w 1 1 t i m e r 1 s t o p ( t w 1 a i n s t r u c t i o n ) p r e s c a l e r s t o p p r e s c a l e r d i v i d e d b y 1 6 s e l e c t e d c o u n t s t a r t s y n c h r o n o u s c i r c u i t s e l e c t e d 0 ? s e t t i m e r v a l u e t i m e r 1 c o u n t t i m e i s s e t . t i m e r 1 r e l o a d r e g i s t e r r 1 52 16 timer count value 82 set ( t1ab instruction) b3 b0 ? set port p1 3 /int pin is set to int input. port p1 3 output latch ? ? ? input mode is set ( op1a instruction) ? clear interrupt request timer 1 interrupt activated condition is cleared. t i m e r 1 i n t e r r u p t r e q u e s t f l a g t 1 f 0 timer 1 interrupt activated condition cleared ( snzt1 instruction) n o t e w h e n t h e i n t e r r u p t r e q u e s t i s c l e a r e d w h e n ? i s e x e c u t e d , c o n s i d e r i n g t h e s k i p o f t h e n e x t i n s t r u c t i o n a c c o r d i n g t o t h e i n t e r r u p t r e q u e s t f l a g t 1 f , i n s e r t t h e n o p i n s t r u c t i o n a f t e r t h e s n z t 1 i n s t r u c t i o n . b3 b0 0 0 ? i n i t i a l i z e v a l i d w a v e f o r m i n t p i n i s i n i t i a l i z e d . i n t p i n i n p u t d i s a b l e d , t i m e r 1 c o n t r o l d i s a b l e d . i n t e r r u p t c o n t r o l r e g i s t e r i 1 ? i n t p i n i n p u t d i s a b l e d ( t i 1 a i n s t r u c t i o n ) t i m e r 1 c o n t r o l d i s a l b e d ? b3 b0 1 1 ? s t a r t t i m e r o p e r a t i o n t i m e r 1 a n d p r e s c a l e r t e m p o r a r i l y s t o p p e d a r e r e s t a r t e d . timer control register w1 1 t i m e r 1 o p e r a t i n g ( t w 1 a i n s t r u c t i o n ) p r e s c a l e r o p e r a t i n g 1 1 c o n t i n u e t o f i g u r e 2 . 3 . 7 o n t h e n e x t p a g e .
2.3 timers 2-31 4502 group application rev.2.01 feb 02, 2005 rej09b0193-0201 fig. 2.3.7 timer start by external input setting example (2) b 3b0 1 ? s e t v a l i d w a v e f o r m v a l i d w a v e f o r m o f i n t p i n i s s e l e c t e d . i n t p i n i n p u t e n a b l e d , r i s i n g s e l e c t e d , t i m e r 1 c o n t r o l i s e n a b l e d . interrupt control register i1 1 rising edge detected ( ti1a instruction) 1 0 b3 b 0 1 e n a b l e i n t e r r u p t s t h e t i m e r 1 i n t e r r u p t w h i c h i s t e m p o r a r i l y d i s a b l e d i s e n a b l e d . interrupt control register v1 1 timer 1 interrupt occurrence enabled ( tv1a instruction) all interrupts enabled ( ei instruction) ?? ? timer start by external input ? : i t c a n b e 0 o r 1 . i n t e r r u p t e n a b l e f l a g i n t e b 3b0 ? ? s e t a u t o - s t o p c i r c u i t t i m e r 1 c o u n t a u t o - s t o p i s s e l e c t e d . interrupt control register w2 ? timer 1 count auto-stop selected ( tw2a instruction) 1 ? ? c l e a r i n t e r r u p t r e q u e s t i n t i n t e r r u p t a c t i v a t e d c o n d i t i o n i s c l e a r e d . e x t e r n a l 0 i n t e r r u p t r e q u e s t f l a g e x f 0 0 int interrupt activated condition cleared ( snz0 instruction) n o t e w h e n t h e i n t e r r u p t r e q u e s t i s c l e a r e d w h e n ? i s e x e c u t e d , c o n s i d e r i n g t h e s k i p o f t h e n e x t i n s t r u c t i o n a c c o r d i n g t o t h e i n t e r r u p t r e q u e s t f l a g e x f 0 , i n s e r t t h e n o p i n s t r u c t i o n a f t e r t h e s n z 0 i n s t r u c t i o n . 1 1 c o n t i n u e d f r o m f i g u r e 2 . 3 . 6 o n t h e p r e c e d i n g p a g e .
2.3 timers 2-32 rev.2.01 feb 02, 2005 4502 group application rej09b0193-0201 fig. 2.3.8 watchdog timer setting example main routine (every 20 ms) ? r e s e t f l a g w d f 1 w a t c h d o g t i m e r f l a g w d f 1 i s r e s e t . 0 w a t c h d o g t i m e r f l a g w d f 1 c l e a r e d ( w r s t i n s t r u c t i o n ) m a i n r o u t i n e e x e c u t i o n r e p e a t do not clear watchdog timer flag wdf1 in interrupt service routine. interrupt may be executed even if program run-away occurs. w h e n g o i n g t o r a m b a c k - u p m o d e wrst ; wdf flag cleared nop di ; interrupt disabled epof ; pof instruction enabled pof oscillation stop (ram back-up mode) i n t h e r a m b a c k - u p m o d e , w e f , w d f 1 a n d w d f 2 f l a g s a r e i n i t i a l i z e d . h o w e v e r , w h e n w d f 2 f l a g i s s e t t o 1 , a t t h e s a m e t i m e , s y s t e m e n t e r s r a m b a c k - u p m o d e , m i c r o c o m p u t e r m a y b e r e s e t . w h e n w a t c h d o g t i m e r a n d r a m b a c k - u p m o d e a r e u s e d , e x e c u t e t h e w r s t i n s t r u c t i o n b e f o r e s y s t e m e n t e r s t h e r a m b a c k - u p m o d e t o i n i t i a l i z e w d f 1 f l a g . n o t e w h e n t h e w a t c h d o g t i m e r f l a g i s c l e a r e d w h e n ? i s e x e c u t e d , c o n s i d e r i n g t h e s k i p o f t h e n e x t i n s t r u c t i o n a c c o r d i n g t o t h e w a t c h d o g t i m e r f l a g w d f 1 , i n s e r t t h e n o p i n s t r u c t i o n a f t e r t h e w r s t i n s t r u c t i o n . 2.3.4 notes on use (1) prescaler stop the prescaler operation to change its frequency dividing ratio. (2) count source stop timer 1 or 2 counting to change its count source. (3) reading the count values stop timer 1 or 2 counting and then execute the tab1 or tab2 instruction to read its data.
2.3 timers 2-33 4502 group application rev.2.01 feb 02, 2005 rej09b0193-0201 (4) writing to the timer stop timer 1 or 2 counting and then execute the t1ab or t2ab instruction to write its data. (5) writing to reload register r1 when writing data to reload register r1 while timer 1 is operating, avoid a timing when timer 1 underflow. (6) timer 1 and timer 2 count start timing and count time when operation starts count starts from the first rising edge of the count source (2) after timer 1 and timer 2 operations start (1). time to first underflow (3) is shorter (for up to 1 period of the count source) than time among next underflow (4) by the timing to start the timer and count source operations after count starts. when selecting cntr input as the count source of timer 2, timer 2 operates synchronizing with the falling edge of cntr input. parameter timer external input period (h and l pulse width) condition high-speed mode middle-speed mode low-speed mode default mode min. 3/f(x in ) 6/f(x in ) 12/f(x in ) 24/f(x in ) unit s typ. max. rating value fig. 2.3.9 timer count start timing and count time when operation starts (t1, t2) (1) timer count source timer value timer underflow signal 321 032 103 2 count source (cntr input) (2) (3) (4) (7) watchdog timer the watchdog timer function is valid after system is released from reset. when not using the watchdog timer function, execute the dwdt instruction and the wrst instruction continuously, and clear the wef flag to 0 to stop the watchdog timer function. the watchdog timer function is valid after system is returned from the ram back-up. when not using the watchdog timer function, execute the dwdt instruction and the wrst instruction continu- ously every system is returned from the ram back-up, and stop the watchdog timer function. (8) pulse width input to cntr pin table 2.3.5 shows the recommended operating condition of pulse width input to cntr pin. table 2.3.5 recommended operating condition of pulse width input to cntr pin
2.4 a/d converter 2-34 rev.2.01 feb 02, 2005 4502 group application rej09b0193-0201 2.4 a/d converter the 4502 group has a 4-channel a/d converter with the 10-bit successive comparison method. this a/d converter can also be used as a comparator to compare analog voltages input from the analog input pin with preset values. this section describes the related registers, application examples using the a/d converter and notes. figure 2.4.1 shows the a/d converter block diagram. fig. 2.4.1 a/d converter structure v ss v dd dac da converter tabad 1 / 6 q1 3 q 1 1 q 1 0 q 1 2 tadab 0 1 4 4 4 4 8 8 8 01 1 8 10 q 1 3 q1 3 0 1 q 1 3 8 (note 1) 8 2 tala q 1 3 taq1 tq1a a d f ( 1 ) p2 0 /a in0 2 1 0 10 p2 1 /a in1 p3 0 /a in2 p 3 1 / a i n 3 i a p 3 ( p 3 0 , p 3 1 ) o p 3 a ( p 3 0 , p 3 1 ) i a p 2 ( p 2 0 , p 2 1 ) o p 2 a ( p 2 0 , p 2 1 ) r e g i s t e r a ( 4 ) r e g i s t e r b ( 4 ) dac operation signal c o m p a r a t o r 4 - c h a n n el m u l t i - p l e x e d an a l o g s w i t c h i n s t r u c t i o n c l o c k a / d c o n t r o l c i r c u i t successive comparison register (ad) (10) a/d interrupt c o m p a r a t o r r e g i s t e r ( 8 ) n o t e s 1 : t h i s s w i t c h i s t u r n e d o n o n l y w h e n a / d c o n v e r t e r i s o p e r a t i n g a n d g e n e r a t e s t h e c o m p a r i s o n v o l t a g e . 2 : w r i t i n g / r e a d i n g d a t a t o t h e c o m p a r a t o r r e g i s t e r i s p o s s i b l e o n l y i n t h e c o m p a r a t o r m o d e ( q 1 3 = 1 ) . t h e v a l u e o f t h e c o m p a r a t o r r e g i s t e r i s r e t a i n e d e v e n w h e n t h e m o d e i s s w i t c h e d t o t h e a / d c o n v e r s i o n m o d e ( q 1 3 = 0 ) b e c a u s e i t i s s e p a r a t e d f r o m t h e s u c c e s s i v e c o m p a r i s o n r e g i s t e r ( a d ) . a l s o , t h e r e s o l u t i o n i n t h e c o m p a r a t o r m o d e i s 8 b i t s b e c a u s e t h e c o m p a r a t o r r e g i s t e r c o n s i s t s o f 8 b i t s . (note 2)
2.4 a/d converter 2-35 4502 group application rev.2.01 feb 02, 2005 rej09b0193-0201 2.4.1 related registers (1) a/d control register q1 a/d operation mode control bit and analog input pin selection bits are assigned to register q1. set the contents of this register through register a with the tq1a instruction. the taq1 instruction can be used to transfer the contents of register q1 to register a. table 2.4.1 shows the a/d control register q1. table 2.4.1 a/d control register q1 a/d control register q1 at reset : 0000 2 at ram back-up : state retained r/w a/d operation mode control bit not used analog input pin selection bits q1 3 q1 2 0 1 0 1 notes 1: r represents read enabled, and w represents write enabled. 2: when a/d converter is used, q1 2 is not used. 2.4.2 a/d converter application examples (1) a/d conversion mode outline: analog input signal from a sensor can be converted into digital values. specifications: analog voltage values from a sensor is converted into digital values by using a 10- bit successive comparison method. use the a in0 pin for this analog input. figure 2.4.2 shows the a/d conversion mode setting example. q1 1 0 0 1 1 a/d conversion mode comparator mode this bit has no function, but read/write is enabled. q1 0 0 1 0 1 selected pins a in0 a in1 a in2 a in3 q1 1 q1 0
2.4 a/d converter 2-36 rev.2.01 feb 02, 2005 4502 group application rej09b0193-0201 fig. 2.4.2 a/d conversion mode setting example b3 b0 ? d i s a b l e i n t e r r u p t s a / d i n t e r r u p t i s t e m p o r a r i l y d i s a b l e d . i n t e r r u p t e n a b l e f l a g i n t e i n t e r r u p t c o n t r o l r e g i s t e r v 2 0 ? ? all interrupts disabled ( di instruction) a/d interrupt occurrence disabled ( tv2a instruction) 0 ? ? s e t a / d c o n v e r t e r a / d c o n v e r s i o n m o d e i s s e l e c t e d t o a / d o p e r a t i o n m o d e . a n a l o g i n p u t p i n a i n 0 i s s e l e c t e d . a/d control register q1 a/d conversion mode, a in0 selected ( tq1a instruction) b3 b 0 ? 0 0 0 c l e a r i n t e r r u p t r e q u e s t a / d i n t e r r u p t a c t i v a t e d c o n d i t i o n i s c l e a r e d . a / d c o n v e r s i o n c o m p l e t i o n f l a g a d f 0 a/d conversion interrupt activated condition cleared ( snzad instruction) n o t e w h e n t h e i n t e r r u p t r e q u e s t i s c l e a r e d w h e n ? i s e x e c u t e d , c o n s i d e r i n g t h e s k i p o f t h e n e x t i n s t r u c t i o n a c c o r d i n g t o t h e f l a g a d f , i n s e r t t h e n o p i n s t r u c t i o n a f t e r t h e s n z a d i n s t r u c t i o n . w h e n i n t e r r u p t i s n o t u s e d when interrupt is used ? s e t i n t e r r u p t i n t e r r u p t s e x c e p t a / d c o n v e r s i o n i s e n a b l e d ( e i i n s t r u c t i o n ) ? set interrupt a/d conversion interrupt temporarily disabled is enabled. b3 b 0 1 ??? interrupt control register v2 a/d interrupt occurrence enabled ( tv2a instruction) interrupt enable flag inte 1 all interrupts enabled ( ei instruction) ? s t a r t a / d c o n v e r s i o n a / d c o n v e r s i o n o p e r a t i o n i s s t a r t e d ( a d s t i n s t r u c t i o n ) . when interrupt is not used w h e n i n t e r r u p t i s u s e d ? c h e c k a / d i n t e r r u p t r e q u e s t a / d c o n v e r s i o n c o m p l e t i o n f l a g i s c h e c k e d ( s n z a d i n s t r u c i t o n ) ? a / d c o n v e r s i o n i n t e r r u p t o c c u r ? e x e c u t e a / d c o n v e r s i o n h i g h - o r d e r 8 b i t s o f r e g i s t e r a d r e g i s t e r a a n d r e g i s t e r b ( t a b a d i n s t r u c t i o n ) l o w - o r d e r 2 b i t s o f r e g i s t e r a d h i g h - o r d e r 2 b i t s o f r e g i s t e r a ( t a l a i n s t r u c t i o n ) 0 i s s e t t o l o w - o r d e r 2 b i t s o f r e g i s t e r a ? : i t c a n b e 0 o r 1 . w h e n a / d c o n v e r s i o n i s e x e c u t e d b y t h e s a m e c h a n n e l , ? t o ? i s r e p e a t e d . w h e n a / d c o n v e r s i o n i s e x e c u t e d b y t h e a n o t h e r c h a n n e l , ? t o ? i s r e p e a t e d .
2.4 a/d converter 2-37 4502 group application rev.2.01 feb 02, 2005 rej09b0193-0201 2.4.3 notes on use (1) note when the a/d conversion starts again when the a/d conversion starts again with the adst instruction during a/d conversion, the previous input data is invalidated and the a/d conversion starts again. (2) a/d converter-1 each analog input pin is equipped with a capacitor which is used to compare the analog voltage. accordingly, when the analog voltage is input from the circuit with high-impedance and, charge/ discharge noise is generated and the sufficient a/d accuracy may not be obtained. therefore, reduce the impedance or, connect a capacitor (0.01 f to 1 f) to analog input pins. figure 2.4.3 shows the analog input external circuit example-1. when the overvoltage applied to the a/d conversion circuit may occur, connect an external circuit in order to keep the voltage within the rated range as shown the figure 2.4.4. in addition, test the application products sufficiently. fig. 2.4.3 analog input external circuit example-1 (3) notes for the use of a/d conversion 2 when the operating mode of the a/d converter is changed from the comparator mode to the a/d conversion mode with bit 3 of register q1 in a program, be careful about the following notes. clear bit 2 of register v2 to 0 to change the operating mode of the a/d converter from the comparator mode to the a/d conversion mode with bit 3 of register q1 (refer to figure 2.4.5 ? ). the a/d conversion completion flag (adf) may be set when the operating mode of the a/d converter is changed from the comparator mode to the a/d conversion mode. accordingly, set a value to bit 3 of register q1, and execute the snzad instruction to clear the adf flag. do not change the operating mode (both a/d conversion mode and comparator mode) of a/d converter with bit 3 of register q1 during operating the a/d converter. fig. 2.4.4 analog input external circuit example-2 fig. 2.4.5 a/d converter operating mode program example clear bit 2 of register v2 to 0 ....... ? change of the operating mode of the a/d converter from the comparator mode to the a/d conversion mode clear the adf flag to 0 with the snzad instruction execute the nop instruction for the case when a skip is performed with the snzad instruction sensor a in ( note ) n o t e : a p p l y t h e v o l t a g e w i t h i n t h e s p e c i f i c a t i o n s t o a n a n a l o g i n p u t p i n . s e n s o r a in about 1 k ?
2.4 a/d converter 2-38 rev.2.01 feb 02, 2005 4502 group application rej09b0193-0201 (4) a/d converter is used at the comparator mode the analog input voltage is higher than the comparison voltage as a result of comparison, the contents of adf flag retains 0, not set to 1. in this case, the a/d interrupt does not occur even when the usage of the a/d interrupt is enabled. accordingly, consider the time until the comparator operation is completed, and examine the state of adf flag by software. the comparator operation is completed after 8 machine cycles. (5) analog input pins even when p2 0 /a in0 , p2 1 /a in1 , p3 0 /a in2 and p3 1 /a in3 are set to pins for analog input, they continue to function as p2 and p3 i/o. accordingly, when any of them are used as these ports and others are used as analog input pins, make sure to set the outputs of pins that are set for analog input to 1. also, the port input function of the pin functions as an analog input is undefined. (6) tala instruction when the tala instruction is executed, the low-order 2 bits of register ad is transferred to the high- order 2 bits of register a, and simultaneously, the low-order 2 bits of register a is 0. (7) recommended operating conditions when using a/d converter the recommended operating conditions of supply voltage and system clock frequency when using a/ d converter are different from those when not using a/d converter. table 2.4.2 shows the recommended operating conditions when using a/d converter. table 2.4.2 recommended operating conditions (when using a/d converter) parameter system clock frequency (at ceramic resonance or rc oscillation) ( note 2 ) system clock frequency (ceramic resonance selected, at external clock input) condition v dd = vrst to 5.5 v (high-speed mode) v dd = vrst to 5.5 v (middle-speed mode) v dd = vrst to 5.5 v (low-speed mode) v dd = vrst to 5.5 v (default mode) v dd = vrst to 5.5 v (high-speed mode) v dd = vrst to 5.5 v (middle-speed mode) v dd = vrst to 5.5 v (low-speed mode) v dd = vrst to 5.5 v (default mode) limits min. 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 max. 4.4 2.2 1.1 0.5 3.2 1.6 0.8 0.4 unit mhz typ. duty 40 % to 60 % notes 1: vrst: detection voltage of voltage drop detection circuit. 2: the frequency at rc oscillation is affected by a capacitor, a resistor and a microcomputer. so, set the constants within the range of the frequency limits.
2-39 4502 group application rev.2.01 feb 02, 2005 rej09b0193-0201 2.5 reset system reset is performed by applying l level to the reset pin for 1 machine cycle or more when the following conditions are satisfied: the value of supply voltage is the minimum value or more of the recommended operating conditions oscillation is stabilized. then when h level is applied to reset pin, the software starts from address 0 in page 0 after elapsing of the internal oscillation stabilizing time (on-chip oscillator (internal oscillator) clock is counted for 5359 times). figure 2.5.2 shows the oscillation stabilizing time. 2.5.1 reset circuit the 4502 group has the voltage drop detection circuit. (1) power-on reset reset can be automatically performed at power on (power-on reset) by the built-in power-on reset circuit. when the built-in power-on reset circuit is used, the time for the supply voltage to rise from 0 v to 2.0 v must be set to 100 s or less. if the rising time exceeds 100 s, connect a capacitor between the reset pin and v ss at the shortest distance, and input l level to reset pin until the value of supply voltage reaches the minimum operating voltage. fig. 2.5.1 structure of reset pin and its peripherals, and power-on reset operation fig. 2.5.2 oscillation stabilizing time after system is released from reset 2.5 reset r e s e t p i n wef watchdog reset signal ( n o t e 1 ) pull-up transistor ( note 1 ) power-on reset circuit v o l g a t e d r o p d e t e c t i o n c i r c u i t v dd ( note 3 ) 1 0 0 s o r l e s s ( note 2 ) internal reset signal p o w e r - o n reset released i n t e r n a l r e s e t s i g n a l r e s e t s t a t e notes 1: t h i s s y m b o l r e p r e s e n t s a p a r a s i t i c d i o d e . 2 : a p p l i e d p o t e n t i a l t o r e s e t p i n m u s t b e v d d o r l e s s . 3 : k e e p t h e v a l u e o f s u p p l y v o l t a g e t o t h e m i n i m u m v a l u e o r m o r e o f t h e r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s . p o w e r - o n r e s e t c i r c u i t o u t p u t r e s e t 0 . 3 v d d 0.85v dd ( n o t e ) n o t e : k e e p t h e v a l u e o f s u p p l y v o l t a g e t o t h e m i n i m u m v a l u e o r m o r e o f t h e r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s . r e s e t i n p u t 1 m a c h i n e c y c l e o r m o r e = program starts (address 0 in page 0) o n - c h i p o s c i l l a t o r ( i n t e r n a l o s c i l l a t o r ) i s c o u n t e d 5 3 5 9 t i m e s .
2-40 rev.2.01 feb 02, 2005 4502 group application rej09b0193-0201 program counter (pc) ............................................................................................ address 0 in page 0 is set to program counter. interrupt enable flag (inte) ................................................................................... power down flag (p) ............................................................................................... external 0 interrupt request flag (exf0) ................................................................ interrupt control register v1 ................................................................................... interrupt control register v2 ................................................................................... interrupt control register i1 .................................................................................... timer 1 interrupt request flag (t1f) ...................................................................... timer 2 interrupt request flag (t2f) ...................................................................... a/d conversion completion flag adf ..................................................................... watchdog timer flags (wdf1, wdf2) ................................................................... watchdog timer enable flag (wef) ....................................................................... timer control register w1 ...................................................................................... timer control register w2 ...................................................................................... timer control register w6 ...................................................................................... clock control register mr ...................................................................................... key-on wakeup control register k0 ....................................................................... key-on wakeup control register k1 ....................................................................... key-on wakeup control register k2 ....................................................................... pull-up control register pu0 ................................................................................... pull-up control register pu1 ................................................................................... pull-up control register pu2 ................................................................................... a/d control register q1 .......................................................................................... carry flag (cy) ....................................................................................................... register a .............................................................................................................. register b .............................................................................................................. register d .............................................................................................................. register e .............................................................................................................. register x .............................................................................................................. register y .............................................................................................................. register z ............................................................................................................... stack pointer (sp) .................................................................................................. operation source clock ................................. on-chip oscillator (operation state) ceramic resonator ........................................................................ operation state rc oscillation circuit ............................................................................. stop state 2.5.2 internal state at reset figure 2.5.3 shows the internal state at reset. the contents of timers, registers, flags and ram other than shown in figure 2.5.3 are undefined, so that set them to initial values. fig. 2.5.3 internal state at reset ? represents undefined. 2.5 reset 00000000000000 ???????? 0 (interrupt disabled) 0 0 0 0 0 0 (interrupt disabled) 0 0 0 0 (interrupt disabled) 0 000 0 0 0 0 1 0 0 0 0 (prescaler, timer 1 stopped) 0 0 0 0 (timer 2 stopped) 0000 1100 0000 0000 0000 0000 0000 0000 0000 0 0000 0000 ??? 0000 0 000 ?? 111
2-41 4502 group application rev.2.01 feb 02, 2005 rej09b0193-0201 2.5.3 notes on use (1) register initial value the initial value of the following registers are undefined after system is released from reset. after system is released from reset, set initial values. register z (2 bits) register d (3 bits) register e (8 bits) (2) power-on reset reset can be automatically performed at power on (power-on reset) by the built-in power-on reset circuit. when the built-in power-on reset circuit is used, the time for the supply voltage to rise from 0 v to 2.0 v must be set to 100 s or less. if the rising time exceeds 100 s, connect a capacitor between the reset pin and v ss at the shortest distance, and input l level to reset pin until the value of supply voltage reaches the minimum operating voltage. 2.5 reset
2-42 rev.2.01 feb 02, 2005 4502 group application rej09b0193-0201 2.6 voltage drop detection circuit 2.6 voltage drop detection circuit the built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value. figure 2.6.1 shows the voltage drop detection circuit, and figure 2.6.2 shows the operation waveform example of the voltage drop detection circuit. fig. 2.6.1 voltage drop detection circuit fig. 2.6.2 voltage drop detection circuit operation waveform example note: refer to section 3.1 electrical characteristics for the reset voltage of the voltage drop detection circuit. + vrst v d d q s r reset signal return input e p o f i n s t r u c t i o n + p o f 2 i n s t r u c t i o n ( c o n t i n u o u s e x e c u t i o n ) ( note 2 ) voltage drop detection circuit reset signal ( n o t e 1 ) v o l t a g e d r o p d e t e c t i o n c i r c u i t n o t e s 1 : i n t h e r a m b a c k - u p m o d e b y t h e p o f 2 i n s t r u c t i o n , t h e v o l t a g e d r o p d e t e c t i o n c i r c u i t s t o p s . 2 : w h e n t h e v d d ( s u p p l y v o l t a g e ) i s v r s t ( d e t e c t i o n v o l t a g e ) o r l e s s , t h e v o l t a g e d r o p d e t e c t i o n c i r c u i t r e s e t s i g n a l i s o u t p u t . v dd the microcomputer starts operation after the on-chip oscillator (internal oscillator) is counted 5359 times. note 3 voltage drop detection circuit reset signal reset pin notes 1: after system is released from reset, the on-chip oscillator (internal oscillator) is selected as the operation clock of the microcomputer. 2: refer to the voltage drop detection circuit characteristics in the electrical characteristics for the rating value of vrst (detection voltage). 3: the vrst (detection voltage) does not include hysteresis. vrst (detection voltage)
2.7 ram back-up 2-43 4502 group application rev.2.01 feb 02, 2005 rej09b0193-0201 2.7 ram back-up 2.7.1 ram back-up mode the system enters ram back-up mode when the pof or pof2 instruction is executed after the epof instruction is executed. table 2.7.1 shows the function and state retained at ram back-up mode. also, table 2.7.2 shows the return source from this state. (1) ram back-up mode as oscillation stops with ram, the state of reset circuit retained, current dissipation can be reduced without losing the contents of ram. table 2.7.1 functions and states retained at ram back-up mode notes 1: o represents that the function can be retained, and ? represents that the function is initialized. registers and flags other than the above are undefined at ram back-up, and set an initial value after returning. 2: the stack pointer (sp) points the level of the stack register and is initialized to 7 at ram back-up. 3: the state of the timer is undefined. 4: initialize the watchdog timer flag wdf1 with the wrst instruction, and then execute the pof or pof2 instruction. 5: the voltage drop detection circuit is operating at the ram back-up state and sytem reset occurs when the voltage drop is detected. 6: as for the d 2 /c pin, the output latch of port c is set to 1 at the ram back-up. however, the output latch of port d 2 is retained. as for the other ports, their output levels are retained at the ram back-up. function program counter (pc), registers a, b, carry flag (cy), stack pointer (sp) ( note 2 ) contents of ram port level selected oscillation circuit timer control register w1 timer control registers w2, w6 clock control register mr interrupt control registers v1, v2 interrupt control register i1 timer 1 function timer 2 function a/d function voltage drop detection circuit pull-up control registers pu0 pu2 key-on wakeup control registers k0 k2 a/d control register q1 external 0 interrupt request flag (exf0) timer 1 interrupt request flag (t1f) timer 2 interrupt request flag (t2f) a/d conversion completion flag (adf) watchdog timer flags (wdf1) watchdog timer enable flag (wef) 16-bit timer (wdt) interrupt enable flag (inte) pof ? o ( note 6 ) o ? o ? ? o ? ( note 3 ) ? o ( note 5 ) o o o ? ? ( note 3 ) ? ? ( note 4 ) ? ? ( note 4 ) ? ram back-up pof2 ? o ( note 6 ) o ? o ? ? o ? ( note 3 ) ? ? o o o ? ? ( note 3 ) ? ? ( note 4 ) ? ? ( note 4 ) ?
2.7 ram back-up 2-44 rev.2.01 feb 02, 2005 4502 group application rej09b0193-0201 remarks key-on wakeup function can be selected with every one port. set the port using the key-on wakeup function to h level before going into the ram back-up state. select the return level ( l level or h level) with the bit 2 of register i1 according to the external state before going into the ram back- up state. return condition return by an external l level input. return by an external h level or l level input. the return level can be selected by register i1 2 . when the return level is input, the exf0 flag is not set. table 2.7.2 return source and return condition note: when the bit 3 (k1 3 ) of the key-on wakeup control register k1 is 0 , the key-on wakeup ( h level or l level) of int pin is set. when the k1 3 is 1 , the key-on wakeup ( l level) of port p1 3 is set. (2) start condition identification when system returns from both ram back-up mode and reset, software is started from address 0 in page 0. the start condition (warm start or cold start) can be identified by examining the state of the power down flag (p) with the snzp instruction. table 2.7.3 start condition identification fig. 2.7.1 start condition identified example return source port p0 port p1 ( note ) port p2 port d 2 /c port d 3 /k port p1 3 /int ( note ) external wakeup signal return condition external wakeup signal input reset p flag 1 0 program start p = 1 ? yes warm start cold start no
2.7 ram back-up 2-45 4502 group application rev.2.01 feb 02, 2005 rej09b0193-0201 2.7.2 related registers (1) key-on wakeup control register k0 register k0 controls the on/off of the key-on wakeup function of ports p0 0 p0 3 . set the contents of this register through register a with the tk0a instruction. the contents of register k0 is transferred to register a with the tak0 instruction. table 2.7.4 shows the key-on wakeup control register k0. table 2.7.4 key-on wakeup control register k0 key-on wakeup control register k0 at reset : 0000 2 at ram back-up : state retained r/w key-on wakeup invalid key-on wakeup valid key-on wakeup invalid key-on wakeup valid key-on wakeup invalid key-on wakeup valid key-on wakeup invalid key-on wakeup valid port p0 3 key-on wakeup control bit port p0 2 key-on wakeup control bit port p0 1 key-on wakeup control bit port p0 0 key-on wakeup control bit 0 1 0 1 0 1 0 1 k0 3 k0 2 k0 1 k0 0 note: r represents read enabled, and w represents write enabled. (2) key-on wakeup control register k1 register k1 controls the on/off of the key-on wakeup function of ports p1 0 p1 3 . set the contents of this register through register a with the tk1a instruction. the contents of register k1 is transferred to register a with the tak1 instruction. table 2.7.5 shows the key-on wakeup control register k1. table 2.7.5 key-on wakeup control register k1 key-on wakeup control register k1 at reset : 0000 2 at ram back-up : state retained r/w p1 3 key-on wakeup invalid/int pin key-on wakeup valid p1 3 key-on wakeup valid/int pin key-on wakeup invalid key-on wakeup invalid key-on wakeup valid key-on wakeup invalid key-on wakeup valid key-on wakeup invalid key-on wakeup valid port p1 3 /int key-on wakeup control bit port p1 2 /cntr key-on wakeup control bit port p1 1 key-on wakeup control bit port p1 0 key-on wakeup control bit 0 1 0 1 0 1 0 1 k1 3 k1 2 k1 1 k1 0 note: r represents read enabled, and w represents write enabled.
2.7 ram back-up 2-46 rev.2.01 feb 02, 2005 4502 group application rej09b0193-0201 pull-up control register pu0 at reset : 0000 2 at ram back-up : state retained w pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on port p0 3 pull-up transistor control bit port p0 2 pull-up transistor control bit port p0 1 pull-up transistor control bit port p0 0 pull-up transistor control bit 0 1 0 1 0 1 0 1 pu0 3 pu0 2 pu0 1 pu0 0 note: w represents write enabled. (4) pull-up control register pu0 register pu0 controls the on/off of the ports p0 0 p0 3 pull-up transistor. set the contents of this register through register a with the tpu0a instruction. table 2.7.7 shows the pull-up control register pu0. table 2.7.7 pull-up control register pu0 (3) key-on wakeup control register k2 register k2 controls the on/off of the key-on wakeup function of ports p2 0 , p2 1 , d 2 /c and d 3 /k. set the contents of this register through register a with the tk2a instruction. the contents of register k2 is transferred to register a with the tak2 instruction. table 2.7.6 shows the key-on wakeup control register k2. table 2.7.6 key-on wakeup control register k2 key-on wakeup control register k2 at reset : 0000 2 at ram back-up : state retained r/w key-on wakeup invalid key-on wakeup valid key-on wakeup invalid key-on wakeup valid key-on wakeup invalid key-on wakeup valid key-on wakeup invalid key-on wakeup valid port d 3 /k key-on wakeup control bit port d 2 /c key-on wakeup control bit port p2 1 /a in1 key-on wakeup control bit port p2 0 /a in0 key-on wakeup control bit 0 1 0 1 0 1 0 1 k2 3 k2 2 k2 1 k2 0 note: r represents read enabled, and w represents write enabled.
2.7 ram back-up 2-47 4502 group application rev.2.01 feb 02, 2005 rej09b0193-0201 pull-up control register pu2 at reset : 0000 2 at ram back-up : state retained w pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on port d 3 /k pull-up transistor control bit port d 2 /c pull-up transistor control bit port p2 1 /a in1 pull-up transistor control bit port p2 0 /a in0 pull-up transistor control bit 0 1 0 1 0 1 0 1 pu2 3 pu2 2 pu2 1 pu2 0 note: w represents write enabled. (6) pull-up control register pu2 register pu2 controls the on/off of the ports p2 0 , p2 1 , d 2 /c and d 3 /k pull-up transistor. set the contents of this register through register a with the tpu2a instruction. table 2.7.9 shows the pull-up control register pu2. table 2.7.9 pull-up control register pu2 pull-up control register pu1 at reset : 0000 2 at ram back-up : state retained w pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on port p1 3 /int pull-up transistor control bit port p1 2 /cntr pull-up transistor control bit port p1 1 pull-up transistor control bit port p1 0 pull-up transistor control bit 0 1 0 1 0 1 0 1 pu1 3 pu1 2 pu1 1 pu1 0 note: w represents write enabled. (5) pull-up control register pu1 register pu1 controls the on/off of the ports p1 0 p1 3 pull-up transistor. set the contents of this register through register a with the tpu1a instruction. table 2.7.8 shows the pull-up control register pu1. table 2.7.8 pull-up control register pu1
2.7 ram back-up 2-48 rev.2.01 feb 02, 2005 4502 group application rej09b0193-0201 interrupt control register i1 at reset : 0000 2 at ram back-up : state retained r/w int pin input disabled int pin input enabled falling waveform ( l level of int pin is recognized with the snzi0 instruction)/ l level rising waveform ( h level of int pin is recognized with the snzi0 instruction)/ h level one-sided edge detected both edges detected disabled enabled int pin input control bit ( note 2 ) interrupt valid waveform for int pin/return level selection bit ( note 2 ) int pin edge detection circuit control bit int pin timer 1 control enable bit 0 1 0 1 0 1 0 1 i1 3 i1 2 i1 1 i1 0 notes 1: r represents read enabled, and w represents write enabled. 2: when the contents of i1 2 and i1 3 are changed, the external interrupt request flag exf0 may be set. accordingly, after the one instruction is executed, clear exf0 flag with the snz0 instruction while the bit 0 (v1 0 ) of register v1 is 0 . in this time, set the nop instruction after the snz0 instruction, for the case when a skip is performed with the snz0 instruction. (7) interrupt control register i1 the int pin timer 1 control enable bit is assigned to bit 0, int pin edge detection circuit control bit is assigned to bit 1, interrupt valid waveform for int pin/return level selection bit is assigned to bit 2 and int pin input control bit is assigned to bit 3. set the contents of this register through register a with the ti1a instruction. in addition, the tai1 instruction can be used to transfer the contents of register i1 to register a. table 2.7.10 shows the interrupt control register i1. table 2.7.10 interrupt control register i1
2.7 ram back-up 2-49 4502 group application rev.2.01 feb 02, 2005 rej09b0193-0201 2.7.3 notes on use (1) key-on wakeup function after setting ports (p0, p1, d 2 /c, d 3 /k, p2 0 /a in0 and p2 1 /a in1 specified with register k0 k2) which key-on wakeup function is valid to h, execute the pof or pof2 instruction. if one of ports which key-on wakeup function is valid is in the l level state, system returns from the ram back-up after the pof or pof2 instruction is executed. (2) pof instruction, pof2 instruction execute the pof or pof2 instruction immediately after executing the epof instruction to enter the ram back-up state. note that system cannot enter the ram back-up state when executing only the pof or pof2 instruction. be sure to disable interrupts by executing the di instruction before executing the epof instruction and the pof or pof2 instruction. (3) return from ram back-up after system returns from ram back-up, set the undefined registers and flags. the initial value of the following registers are undefined at ram back-up. after system is returned from ram back-up, set initial values. register z (2 bits) register x (4 bits) register y (4 bits) register d (3 bits) register e (8 bits) (4) watchdog timer the watchdog timer function is valid after system is returned from the ram back-up. when not using the watchdog timer function, execute the dwdt instruction and the wrst instruction continuously every system is returned from the ram back-up, and stop the watchdog timer function. (5) p1 3 /int pin when the bit 3 of register i1 is cleared, the ram back-up mode is selected and the input of int pin is disabled, be careful about the following notes. when the key-on wakeup function of port p1 3 is not used (register k1 3 = 0 ), clear bits 2 and 3 of register i1 before system enters to the ram back-up mode. (6) external clock when the external signal clock is used as the source oscillation (f(x in )), note that the ram back- up mode ( pof and pof2 instructions) cannot be used.
2.8 oscillation circuit 2-50 rev.2.01 feb 02, 2005 4502 group application rej09b0193-0201 2.8 oscillation circuit the 4502 group has an internal oscillation circuit to produce the clock required for microcomputer operation. the ceramic resonance and the rc oscillation can be used for the source clock. after system is released from reset, the 4502 group starts operation by the clock output from the on-chip oscillator which is the internal oscillator. fig. 2.8.1 switch to ceramic resonance/rc oscillation r e s e t o n - c h i p o s c i l l a t o r o p e r a t i o n c m c k i n s t r u c t i o n c r c k i n s t r u c t i o n ceramic resonator valid on-chip oscillator stop rc oscillation stop r c o s c i l l a t i o n v a l i d o n - c h i p o s c i l l a t o r s t o p c e r a m i c r e s o n a t o r s t o p 2.8.1 oscillation circuit (1) f(x in ) clock generating circuit the ceramic resonator or rc oscillation can be used for the source oscillation (f(x in )) of the mcu. after system is released from reset, the 4502 group starts operation by the clock output from the on-chip oscillator which is the internal oscillator. when the ceramic resonator is used, execute the cmck instruction. when the rc oscillation is used, execute the crck instruction. the oscillation circuit by the cmck or crck instruction can be selected only at once. the oscillation circuit corresponding to the first executed one of these two instructions is valid. other oscillation circuit and the on-chip oscillator stop. execute the cmck or the crck instruction in the initial setting routine of program (executing it in address 0 in page 0 is recommended). also, when the cmck or the crck instruction is not executed in program, the 4502 group operates by the on-chip oscillator. (2) on-chip oscillator operation when the mcu operates by the on-chip oscillator as the source oscillation (f(x in )) without using the ceramic resonator or the rc oscillator, connect x in pin to v ss and leave x out pin open (figure 2.8.2). the clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. be careful that variable frequencies when designing application products. fig. 2.8.2 handling of x in and x out when operating on-chip oscillator 4 5 0 2 x i n x o u t * d o n o t u s e t h e c m c k i n s t r u c t i o n a n d c r c k i n s t r u c t i o n i n p r o g r a m .
2.8 oscillation circuit 2-51 4502 group application rev.2.01 feb 02, 2005 rej09b0193-0201 (3) ceramic resonator when the ceramic resonator is used as the source oscillation (f(x in )), connect the ceramic resonator and the external circuit to pins x in and x out at the shortest distance. then, execute the cmck instruction. a feedback resistor is built in between pins x in and x out (figure 2.8.3). as for the oscillation frequency, do not exceed the values shown in the table 2.8.1. fig. 2.8.3 ceramic resonator external circuit 4 5 0 2 x i n x out rd c i n c o u t execute the cmck instruction in program. note: externally connect a damping resistor rd depending on the oscillation frequency. (a feedback resistor is built-in.) use the resonator manu- facturer s recommended value because constants such as capacitance depend on the resonator. supply voltage 2.7 v ( note ) to 5.5 v (system clock) (f(x in )) high-speed mode (f(x in )/2) middle-speed mode (f(x in )/4) low-speed mode (f(x in )/8) default mode oscillation frequency 4.4 mhz note: system is in the reset state when the value is under the detection voltage. table 2.8.1 maximum value of oscillation frequency and supply voltage (4) rc oscillation when the rc oscillation is used as the source oscillation (f(x in )), connect the x in pin to the external circuit of resistor r and the capacitor c at the shortest distance and leave x out pin open. then, execute the crck instruction (figure 2.8.4). the frequency is affected by a capacitor, a resistor and a microcomputer. so, set the constants within the range of the frequency limits. fig. 2.8.4 external rc oscillation circuit 4 5 0 2 x i n x o u t r c * e x e c u t e t h e c r c k i n s t r u c t i o n i n p r o g r a m .
2.8 oscillation circuit 2-52 rev.2.01 feb 02, 2005 4502 group application rej09b0193-0201 2.8.2 oscillation operation system clock is supplied to cpu and peripheral device as the standard clock for the microcomputer operation. for the 4502 group, the clock supplied from the on-chip oscillator (internal oscillator) or the ceramic resonance circuit, rc oscillation circuit is selected from the high-speed mode (f(x in )), middle- speed mode (f(x in )/2), low-speed mode (f(x in )/4) or default mode (f(x in )/8) with the register mr. figure 2.8.5 shows the structure of the clock control circuit. fig. 2.8.5 structure of clock control circuit m r 3 , m r 2 0 0 0 1 1 0 1 1 q s qr q s r c r c k i n s t r u c t i o n q s r c m c k i n s t r u c t i o n q s r reset pin x o u t x i n k e y - o n w a k e u p s i g n a l instruction clock c o u n t e r w a i t t i m e ( n o t e 2 ) c o n t r o l c i r c u i t p r o g r a m s t a r t s i g n a l r c o s c i l l a t i o n c i r c u i t d i v i s i o n c i r c u i t d i v i d e d b y 8 d i v i d e d b y 4 d i v i d e d b y 2 i n t e r n a l c l o c k g e n e r a t i o n c i r c u i t ( d i v i d e d b y 3 ) n o t e s 1 : s y s t e m o p e r a t e s b y t h e o n - c h i p o s c i l l a t o r c l o c k ( f ( r i n g ) ) u n t i l t h e c m c k o r c r c k i n s t r u c t i o n i s e x e c u t e d a f t e r s y s t e m i s r e l e a s e d f r o m r e s e t . 2 : t h e w a i t t i m e c o n t r o l c i r c u i t i s u s e d t o g e n e r a t e t h e t i m e r e q u i r e d t o s t a b i l i z e t h e f ( x i n ) o s c i l l a t i o n . a f t e r t h e c e r t a i n o s c i l l a t i o n s t a b i l i z i n g w a i t t i m e e l a p s e s , t h e p r o g r a m s t a r t s i g n a l i s o u t p u t . t h i s c i r c u i t o p e r a t e s w h e n s y s t e m i s r e l e a s e d f r o m r e s e t o r r e t u r n e d f r o m r a m b a c k - u p . system clock o n - c h i p o s c i l l a t o r ( i n t e r n a l o s c i l l a t o r ) ( n o t e 1 ) multiplexer c e r a m i c r e s o n a t o r c i r c u i t pof or epof instruction + pof2 instruction
2.8 oscillation circuit 2-53 4502 group application rev.2.01 feb 02, 2005 rej09b0193-0201 2.8.3 notes on use (1) clock control execute the cmck or the crck instruction in the initial setting routine of program (executing it in address 0 in page 0 is recommended). the oscillation circuit by the cmck or crck instruction can be selected only at once. the oscillation circuit corresponding to the first executed one of these two instructions is valid. other oscillation circuits and the on-chip oscillator stop. (2) on-chip oscillator the clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. be careful that variable frequencies when designing application products. also, the oscillation stabilize wait time after system is released from reset is generated by the on- chip oscillator clock. when considering the oscillation stabilize wait time after system is released from reset, be careful that the variable frequency of the on-chip oscillator clock. (3) external clock when the external signal clock is used as the source oscillation (f(x in )), note that the ram back-up mode ( pof and pof2 instructions) cannot be used. (4) value of a part connected to an oscillator values of a capacitor and a resistor of the oscillation circuit depend on the connected oscillator and the board. accordingly, consult the oscillator manufacturer for values of each part connected the oscillator.
chapter 3 appendix 3.1 electrical characteristics 3.2 typical characteristics 3.3 list of precautions 3.4 notes on noise 3.5 package outline
3.1 electrical characteristics 3-2 rev.2.01 feb 02, 2005 4502 group appendix rej09b0193-0201 3.1 electrical characteristics 3.1.1 absolute maximum ratings table 3.1.1 absolute maximum ratings parameter supply voltage input voltage p0, p1, p2, p3, d 2 /c, d 3 /k, reset , x in input voltage d 0 , d 1 , d 4 , d 5 input voltage a in0 ? in3 output voltage p0, p1, p2, p3, d 2 /c, d 3 /k, reset output voltage d 0 , d 1 , d 4 , d 5 output voltage x out power dissipation operating temperature range storage temperature range conditions output transistors in cut-off state ta = 25 ? symbol v dd v i v i v i v o v o v o p d topr tstg unit v v v v v v v mw ? ? ratings ?.3 to 6.5 ?.3 to v dd +0.3 ?.3 to 13.0 ?.3 to v dd +0.3 ?.3 to v dd +0.3 ?.3 to 13.0 ?.3 to v dd +0.3 300 ?0 to 85 ?0 to 125
3.1 electrical characteristics 3-3 4502 group appendix rev.2.01 feb 02, 2005 rej09b0193-0201 3.1.2 recommended operating conditions table 3.1.2 recommended operating conditions 1 (ta = ?0 ? to 85 ?, v dd = 2.7 to 5.5 v, unless otherwise noted) symbol v dd v ram v ss v ih v ih v ih v ih v ih v il v il v il v il i ol (peak) i ol (peak) i ol (peak) i ol (peak) i ol (avg) i ol (avg) i ol (avg) i ol (avg) i ol (avg) parameter supply voltage ram back-up voltage supply voltage ??level input voltage ??level input voltage ??level input voltage ??level input voltage ??level input voltage ??level input voltage ??level input voltage ??level input voltage ??level input voltage ??level peak output current ??level peak output current ??level peak output current ??level peak output current ??level average output current ??level average output current ??level average output current ??level average output current ??level total average current notes 1: system is in the reset state when the value is the detection voltage of the voltage drop detection circuit or less. 2: the voltage drop detection circuit is operating in the ram back-up with the pof instruction (system enters into the reset st ate when the value is vrst or less). in the ram back-up mode with the pof2 instruction, the voltage drop detection circuit stops. 3: the average output current (i oh , i ol ) is the average value during 100 ms. unit conditions high-speed mode middle-speed mode low-speed mode default mode (at ram back-up mode with the pof2 instruction) p0, p1, p2, p3, d 2 , d 3 , x in d 0 , d 1 , d 4 , d 5 reset c, k cntr, int p0, p1, p2, p3, d 0 ? 5 , x in c, k reset cntr, int p2, p3, reset d 0 , d 1 d 2 /c, d 3 /k, d 4 , d 5 p0, p1 p2, p3, reset (note 3) d 0 , d 1 (note 3) d 2 /c, d 3 /k, d 4 , d 5 (note 3) p0, p1 (note 3) p2, d, reset p0, p1, p3 max. 5.5 v dd 12 v dd v dd v dd v dd 0.2v dd 0.16v dd 0.3v dd 0.15v dd 10 40 24 24 5.0 30 15 12 80 80 limits min. 2.7 (note 1) 1.8 (note 2) 0.8v dd 0.8v dd 0.85v dd 0.5v dd 0.7v dd 0.85v dd 0 0 0 0 typ. 0 f(x in ) 4.4 mhz v dd = 4.0 to 5.5 v v dd = 2.7 to 5.5 v v dd = 5.0 v v dd = 5.0 v v dd = 5.0 v v dd = 5.0 v v dd = 5.0 v v dd = 5.0 v v dd = 5.0 v v dd = 5.0 v v v v v v v v v v v v ma ma ma ma ma ma ma ma ma ma 4.4 f [mhz] f [mhz] ceramic resonator and high-speed mode selected external clock input (ceramic resonator selected) recommended operating condition 4.2 2.7 5.5 v dd [v] v rst (note) 3.2 4.2 2.7 5.5 v dd [v] v rst (note) recommended operating condition it shows the electrical characteristics range of detected voltage for voltage drop detection circuit. system reset occurs when the supply voltage is under the detected voltage for voltage drop detection circuit. note:
3.1 electrical characteristics 3-4 rev.2.01 feb 02, 2005 4502 group appendix rej09b0193-0201 table 3.1.3 recommended operating conditions 2 (ta = 20 c to 85 c, v dd = 2.7 to 5.5 v, unless otherwise noted) f(x in ) f(x in ) ? h and l pulse width) valid supply voltage rising time for power-on reset circuit conditions mhz mhz % hz s c, 20 to 85 c high-speed mode middle-speed mode low-speed mode default mode high-speed mode middle-speed mode low-speed mode default mode v dd = 0
3.1 electrical characteristics 3-5 4502 group appendix rev.2.01 feb 02, 2005 rej09b0193-0201 3.1.3 electrical characteristics table 3.1.4 electrical characteristics (ta = 20 c to 85 c, v dd = 2.7 to 5.5 v, unless otherwise noted) v ol v ol v ol v ol v ol i ih i ih i il i il i dd r pu v t+ v t v t+ v t f(ring) l level output voltage p0, p1 l level output voltage p2, p3, reset l level output voltage d 0 , d 1 l level output voltage d 2 /c, d 3 /k l level output voltage d 4 , d 5 h level input current p0, p1, p2, p3, d 2 /c, d 3 /k, reset h level input current d 0 , d 1 , d 4 , d 5 l level input current p0, p1, p2, p3 l level input current d 0 , d 1 , d 2 /c, d 3 /k, d 4 , d 5 supply current pull-up resistor value p0, p1, p2, d 2 /c, d 3 /k, reset hysteresis int, cntr hysteresis reset on-chip oscillator clock frequency (note 3) at active mode (notes 1, 2) at ram back-up mode (pof instruction execution) at ram back-up mode (pof2 instruction execution) v v v v v ? c v dd = 5.0 v v dd = 3.0 v v i = 0 v, v dd = 5.0 v v dd = 5.0 v v dd = 5.0 v v dd = 5.0 v limits max. 2.0 0.9 2.0 0.6 2.0 0.9 2.0 0.9 2.0 0.9 1.0 1.0 5.0 3.9 3.3 3.0 100 1.0 10 6.0 150 3.0 i ol = 12 ma i ol = 4.0 ma i ol = 5.0 ma i ol = 1.0 ma i ol = 30 ma i ol = 10 ma i ol = 15 ma i ol = 5.0 ma i ol = 15 ma i ol = 5.0 ma min. 1.0 1.0 30 1.0 typ. 1.7 1.3 1.1 1.0 50 0.1 60 0.25 1.2 2.0 high-speed mode middle-speed mode low-speed mode default mode symbol parameter unit notes 1: the operation current of the voltage drop detection circuit is included. 2: when the a/d converter is used, the a/d operation current (ia dd ) is included. 3: when system operates by the on-chip oscillator, the system clock frequency is the on-chip oscillator clock divided by the di viding ratio selected with register mr.
3.1 electrical characteristics 3-6 rev.2.01 feb 02, 2005 4502 group appendix rej09b0193-0201 3.1.4 a/d converter recommended operating conditions table 3.1.5 a/d converter recommended operating conditions (comparator mode included, ta = 20 c to 85 c, unless otherwise noted) symbol v dd v ia f(x in ) parameter supply voltage analog input voltage oscillation frequency table 3.1.6 a/d converter characteristcs (comparator mode included, ta = 20 c to 85 c, unless otherwise noted) conditions unit v v v mhz mhz mhz mhz ta = 25 c ta = 20 c to 85 c v dd = 2.7 to 5.5 v high-speed mode middle-speed mode low-speed mode default mode min. 2.7 (note) 3.0 0 0.1 0.2 0.4 0.8 typ. max. 5.5 5.5 v dd +2lsb limits symbol v 0t v fst ia dd t conv parameter resolution linearity error differential non-linearity error zero transition voltage full-scale transition voltage a/d operating current (note 1) a/d conversion time comparator resolution comparator error (note 2) comparator comparison time test conditions bits lsb lsb mv mv ma c, v dd = 2.7 to 5.5 v ta = 25 c to 85 c, v dd = 3.0 v to 5.5 v ta = 25 c, v dd = 2.7 to 5.5 v ta = 25 c to 85 c, v dd = 3.0 v to 5.5 v v dd = 5.12 v v dd = 5.12 v v dd = 5.0 v f(x in ) = 0.4 mhz to 4.0 mhz f(x in ) = 4.0 mhz high-speed mode middle-speed mode low-speed mode default mode comparator mode v dd = 5.12 v f(x in ) = 4.0 mhz high-speed mode middle-speed mode low-speed mode default mode min. 10 5115 typ. 20 5125 0.3 max. 10 ?.0 ?.9 30 5135 0.9 46.5 93.0 186 372 8 ?0 6.0 12 24 48 limits notes 1: when the a/d converter is used, the ia dd is included to i dd . 2: as for the error from the logic value in the comparator mode, when the contents of the comparator register is n, the logic v alue of the comparison voltage v ref which is generated by the built-in da converter can be obtained by the following formula. logic value of comparison voltage v ref v ref = ?
3.1 electrical characteristics 3-7 4502 group appendix rev.2.01 feb 02, 2005 rej09b0193-0201 3.1.6 basic timing diagram 3.1.5 voltage drop detection circuit characteristics table 3.1.7 voltage drop detection circuit characteristics (ta = 20 c to 85 c, unless otherwise noted) test conditions ta = 25 c ram back-up mode v dd = 5.0 v (pof instruction execution) (note 2) parameter detection voltage (note 1) operation current of voltage drop detection circuit symbol v rst i rst limits unit min. 2.7 3.3 typ. 3.5 50 max. 4.2 3.7 100 v
3.2 typical characteristics 3-8 rev.2.01 feb 02, 2005 4502 group appendix rej09b0193-0201 3.2 typical characteristics the data described below are characteristic examples for the 4502 group. unless otherwise noted, the characteristics for mask rom version are shown here. the data shown here are just characteristics examples and are not guaranteed. for rated values, refer to 3.1 electrical characteristics . standard characteristics are different between mask rom version and one time prom version, due to the difference in the manufacturing processes. even in the mcus which have the same memory type, standard characteristics are different in each sample, too. 3.2.1 v dd ? dd characteristics (1) v dd ? dd characteristics (ta = 25 ?, f(x in ) = 4 mhz, at ceramic resonance) (2) v dd ? dd characteristics (ta = 25 ?, f(x in ) = 2 mhz, at ceramic resonance) v dd [v] high-speed mode middle-speed mode low-speed mode default mode 2.0 1.5 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd [v] high-speed mode middle-speed mode low-speed mode default mode 2.5 2.0 1.5 1.0 0.5 0.0 i dd [ma] i dd [ma] 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
3.2 typical characteristics 3-9 4502 group appendix rev.2.01 feb 02, 2005 rej09b0193-0201 v dd [v] i dd [ma] v dd [v] i dd [ma] (3) v dd ? dd characteristics (ta = 25 ?, f(x in ) = 1 mhz, at ceramic resonance) high-speed mode middle-speed mode low-speed mode default mode high-speed mode middle-speed mode low-speed mode default mode (4) v dd ? dd characteristics (ta = 25 ?, f(x in ) = 400 khz, at ceramic resonance) 2.0 1.5 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.0 1.5 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
3.2 typical characteristics 3-10 rev.2.01 feb 02, 2005 4502 group appendix rej09b0193-0201 resistor r [k ? (5) ri dd characteristics (ta = 25 ?, at rc oscillation, v dd = 5 v, c = 33 pf) high-speed mode middle-speed mode low-speed mode default mode high-speed mode middle-speed mode low-speed mode default mode (6) v dd ? dd characteristics (ta = 25 ?, on-chip oscillator) 2.5 2.0 1.5 1.0 0.5 0.0 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.0 5.0 10.0 15.0 20.0
3.2 typical characteristics 3-11 4502 group appendix rev.2.01 feb 02, 2005 rej09b0193-0201 v dd [v] i dd [na] (7) v dd ? dd characteristics (ta = 25 ?, at ram back-up) 100 80 60 40 20 0 20 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
3.2 typical characteristics 3-12 rev.2.01 feb 02, 2005 4502 group appendix rej09b0193-0201 3.2.2 frequency characteristics (1) on-chip oscillator frequency v dd ?(ring) characteristics v dd [v] ta = 30 c ta = 25 c ta = 95 c f(ring) [mhz] f(ring) [mhz] ta [ c] (2) on-chip oscillator frequency ta?(ring) characteristics (v dd = 5.0 v) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100
3.2 typical characteristics 3-13 4502 group appendix rev.2.01 feb 02, 2005 rej09b0193-0201 (3) rc oscillation frequency (r-f(x in )) characteristics (v dd = 5.0 v, ta = 25 ?, c = 33pf) resistor r [k ? c] (4) rc oscillation frequency (ta-f(x in )) characteristics (v dd = 5.0 v, c = 33pf) 3.3 k ? ? ? ? ? ? 30 20 10 0 10 20 30 40 50 60 70 80 90 100
3.2 typical characteristics 3-14 rev.2.01 feb 02, 2005 4502 group appendix rej09b0193-0201 3.2.3 v ol ? ol characteristics (v dd = 5 v) (1) ports p0, p1 (2) ports p2, p3, reset pin v ol [v] i ol [ma] v ol [v] i ol [ma] ta = 30 c ta = 25 c ta = 95 c ta = 30 c ta = 25 c ta = 95 c 100 90 80 70 60 50 40 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 100 90 80 70 60 50 40 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
3.2 typical characteristics 3-15 4502 group appendix rev.2.01 feb 02, 2005 rej09b0193-0201 (3) ports d 0 , d 1 (4) ports d 2 /c, d 3 /k v ol [v] i ol [ma] v ol [v] i ol [ma] ta = 30 c ta = 25 c ta = 95 c ta = 30 c ta = 25 c ta = 95 c 100 90 80 70 60 50 40 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 100 90 80 70 60 50 40 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
3.2 typical characteristics 3-16 rev.2.01 feb 02, 2005 4502 group appendix rej09b0193-0201 (5) ports d 4 , d 5 v ol [v] i ol [ma] ta = 30 c ta = 25 c ta = 95 c 100 90 80 70 60 50 40 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
3.2 typical characteristics 3-17 4502 group appendix rev.2.01 feb 02, 2005 rej09b0193-0201 3.2.4 input threshold (v ih ? il ) characteristics (ta = 25 ?) (1) ports p0?3, d 2 , d 3 v dd [v] v ihl [v] (2) ports d 0 , d 1 v dd [v] v ihl [v] 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
3.2 typical characteristics 3-18 rev.2.01 feb 02, 2005 4502 group appendix rej09b0193-0201 (3) ports d 4 , d 5 v dd [v] v ihl [v] (4) x in pin v dd [v] v ihl [v] 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
3.2 typical characteristics 3-19 4502 group appendix rev.2.01 feb 02, 2005 rej09b0193-0201 (5) ports c, k v dd [v] v ihl [v] (6) reset pin v dd [v] v ih /v il [v] v ih v il 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
3.2 typical characteristics 3-20 rev.2.01 feb 02, 2005 4502 group appendix rej09b0193-0201 (7) int pin, cntr pin v dd [v] v ih /v il [v] v dd (v) r pu (k ? 3.2.5 v dd ? pu characteristics (ports p0?2, d 2 /c, d 3 /k, reset) ta = 25 c ta = 30 c ta = 95 c v ih v il 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 200 150 100 50 0
3.2 typical characteristics 3-21 4502 group appendix rev.2.01 feb 02, 2005 rej09b0193-0201 3.2.6 analog input current characteristics pins v ain ? ain (v dd = 5 v, high-speed mode, ta = 25 ?) (1) f(x in ) = 4 mhz analog input voltage v ain (v) analog input current i ain (na) (2) f(x in ) = 2 mhz analog input voltage v ain (v) analog input current i ain (na) 200 150 100 50 0 50 100 150 200 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 100 80 60 40 20 0 20 40 60 80 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
3.2 typical characteristics 3-22 rev.2.01 feb 02, 2005 4502 group appendix rej09b0193-0201 (3) f(x in ) = 1 mhz analog input voltage v ain (v) analog input current i ain (na) (4) f(x in ) = 400 khz analog input voltage v ain (v) analog input current i ain (na) 50 40 30 20 10 0 10 20 30 40 50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 20 15 10 5 0 5 10 15 20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
3.2 typical characteristics 3-23 4502 group appendix rev.2.01 feb 02, 2005 rej09b0193-0201 3.2.7 a/d converter operation current (v dd ?i dd ) characteristics (ta = 25 ?) v dd [v] a idd [ 3.2.8 voltage drop detection circuit characteristics (1) detection voltage (mask rom version) ta [ c] v rst [v] 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 600 500 400 300 200 100 0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100
3.2 typical characteristics 3-24 rev.2.01 feb 02, 2005 4502 group appendix rej09b0193-0201 (2) detection voltage (one tim prom version) ta [ c] v rst [v] (3) operation voltage (v dd ? rst ) characteristics ta = 25 ? v dd [v] i rst [ 50 40 30 20 10 0102030405060708090100 5.0 4.5 4.0 3.5 3.0 2.5 2.0
3.2 typical characteristics 3-25 4502 group appendix rev.2.01 feb 02, 2005 rej09b0193-0201 3.2.9 a/d converter typical characteristics fig. 3.2.1 a/d conversion characteristics data figure 3.2.1 shows the a/d accuracy measurement data. (1) non-linearity error ......................... this means a deviation from the ideal characteristics between v 0 to v 1022 of actual a/d conversion characteristics. in figure 3.2.1, it is ( ? ? 1. in figure 3.2.1, this is ? 0 to 1. in figure 3.2.1, this is the value of ? 1022 to 1023. in figure 3.2.1, this is the value of ? ? ? ? ? ? ? ?
3.2 typical characteristics 3-26 rev.2.01 feb 02, 2005 4502 group appendix rej09b0193-0201 -15 -10 -5 0 5 10 15 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 -15 -10 -5 0 5 10 15 256 272 288 304 320 336 352 368 384 400 416 432 448 464 480 496 512 -15 -10 -5 0 5 10 15 512 528 544 560 576 592 608 624 640 656 672 688 704 720 736 752 768 -15 -10 -5 0 5 10 15 768 784 800 816 832 848 864 880 896 912 928 944 960 976 992 1008 1024 (1) v dd = 5.12 v, x in = 4 mhz (high-speed mode), ta = 25 ? 1lsb width error 1lsb width error 1lsb width error 1lsb width error error/1lsb width [mv] error/1lsb width [mv] error/1lsb width [mv] error/1lsb width [mv]
3.3 list of precautions 3-27 4502 group appendix rev.2.01 feb 02, 2005 rej09b0193-0201 3.3 list of precautions 3.3.1 program counter make sure that the pc h does not specify after the last page of the built-in rom. 3.3.2 stack registers (sk s ) stack registers (sks) are eight identical registers, so that subroutines can be nested up to 8 levels. however, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. accordingly, be careful not to over the stack when performing these operations together. 3.3.3 notes on i/o port (1) note when an i/o port is used as an input port set the output latch to 1 and input the port value before input. if the output latch is set to 0, l level can be input. (2) noise and latch-up prevention connect an approximate 0.1 ? the input/output of d 2 , d 3 , p1 2 and p1 3 can be used even when c, k, cntr (input) and int are selected. the input of p1 2 can be used even when cntr (output) is selected. the input/output of p2 0 , p2 1 , p3 0 and p3 1 can be used even when a in0 , a in1 , a in2 and a in3 are selected. (4) connection of unused pins table 3.3.1 shows the connections of unused pins. (5) sd, rd instructions when the sd and rd instructions are used, do not set 0110 2 or more to register y. (6) analog input pins when both analog input a in0 a in3 and i/o ports p2 and p3 function are used, note the following; selection of analog input pins even when p2 0 /a in0 , p2 1 /a in1 , p3 0 /a in2 , p3 1 /a in3 are set to pins for analog input, they continue to function as ports p2 and p3 input/output. accordingly, when any of them are used as i/o port and others are used as analog input pins, make sure to set the outputs of pins that are set for analog input to 1. also, the port input function of the pin functions as an analog input is undefined. (7) notes on port p1 3 /int pin when the bit 3 of register i1 is cleared, the ram back-up mode is selected and the input of int pin is disabled, be careful about the following notes. when the key-on wakeup function of port p1 3 is not used (register k1 3 = 0 ), clear bits 2 and 3 of register i1 before system enters to the ram back-up mode.
3.3 list of precautions 3-28 rev.2.01 feb 02, 2005 4502 group appendix rej09b0193-0201 table 3.3.1 connections of unused pins connection connect to v ss . open. open. (output latch is set to 1. ) open. (output latch is set to 0. ) connect to v ss . open. (output latch is set to 1. ) open. (output latch is set to 0. ) connect to v ss . open. (output latch is set to 1. ) open. (output latch is set to 0. ) connect to v ss . open. (output latch is set to 1. ) open. (output latch is set to 0. ) connect to v ss . open. (output latch is set to 1. ) open. (output latch is set to 0. ) connect to v ss . open. (output latch is set to 1. ) open. (output latch is set to 0. ) connect to v ss . open. (output latch is set to 1. ) open. (output latch is set to 0. ) connect to v ss . pin x in x out d 0 , d 1 d 4 , d 5 d 2 /c d 3 /k p0 0 p0 3 p1 0 , p1 1 p1 2 /cntr p1 3 /int p2 0 /a in0 p2 1 /a in1 p3 0 /a in2 p3 1 /a in3 usage condition system operates by the on-chip oscillator. (note 1) system operates by the external clock. (the ceramic resonator is selected with the cmck instruction.) system operates by the rc oscillator. (the rc oscillation is selected with the crck instruction.) system operates by the on-chip oscillator. (note 1) the key-on wakeup function is not selected. (note 4) the pull-up function and the key-on wakeup function are not selected. (notes 2, 3) the pull-up function and the key-on wakeup function are not selected. (notes 2, 3) the key-on wakeup function is not selected. (note 4) the pull-up function and the key-on wakeup function are not selected. (notes 2, 3) the pull-up function and the key-on wakeup function are not selected. (notes 2, 3) the key-on wakeup function is not selected. (note 4) the pull-up function and the key-on wakeup function are not selected. (notes 2, 3) the pull-up function and the key-on wakeup function are not selected. (notes 2, 3) the key-on wakeup function is not selected. the input to int pin is disabled. (notes 4, 5) the pull-up function and the key-on wakeup function are not selected. (notes 2, 3) the pull-up function and the key-on wakeup function are not selected. (notes 2, 3) the key-on wakeup function is not selected. (note 4) the pull-up function and the key-on wakeup function are not selected. (notes 2, 3) the pull-up function and the key-on wakeup function are not selected. (notes 2, 3) notes 1: when the ceramic resonator or the rc oscillation is not selected by program, system operates by the on-chip oscillator (internal oscillator). 2: when the pull-up function is left valid, the supply current is increased. do not select the pull-up function. 3: when the key-on wakeup function is left valid, the system returns from the ram back-up state immediately after going into the ram back-up state. do not select the key-on wakeup function. 4: when selecting the key-on wakeup function, select also the pull-up function. 5: clear the bit 3 (i1 3 ) of register i1 to 0 to disable to input to int pin (after reset: i1 3 = 0 ) (note when connecting to v ss )
3.3 list of precautions 3-29 4502 group appendix rev.2.01 feb 02, 2005 rej09b0193-0201 3.3.4 notes on interrupt (1) setting of int interrupt valid waveform set a value to the bit 2 of register i1, and execute the snz0 instruction to clear the exf0 flag to 0 after executing at least one instruction. depending on the input state of p1 3 /int pin, the external interrupt request flag (exf0) may be set to 1 when the interrupt valid waveform is changed. (2) setting of int pin input control set a value to the bit 3 of register i1, and execute the snz0 instruction to clear the exf0 flag to 0 after executing at least one instruction. depending on the input state of p1 3 /int pin, the external interrupt request flag (exf0) may be set to 1 when the interrupt valid waveform is changed. (3) multiple interrupts multiple interrupts cannot be used in the 4502 group. (4) notes on interrupt processing when the interrupt occurs, at the same time, the interrupt enable flag inte is cleared to 0 (interrupt disable state). in order to enable the interrupt at the same time when system returns from the interrupt, write ei and rti instructions continuously. (5) p1 3 /int pin note [1] on bit 3 of register i1 when the input of the int pin is controlled with the bit 3 of register i1 in software, be careful about the following notes. depending on the input state of the p1 3 /int pin, the external 0 interrupt request flag (exf0) may be set when the bit 3 of register i1 is changed. in order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register v1 to 0 (refer to figure 3.3.1 ? 0 after executing at least one instruction (refer to figure 3.3.1 ? ? ??? ? ??? ? ? ? fig. 3.3.1 external 0 interrupt program example-1
3.3 list of precautions 3-30 rev.2.01 feb 02, 2005 4502 group appendix rej09b0193-0201 (6) power down instruction be sure to disable interrupts by executing the di instruction before executing the epof instruction. note [2] on bit 3 of register i1 when the bit 3 of register i1 is cleared to 0 , the ram back-up mode is selected and the input of int pin is disabled, be careful about the following notes. when the key-on wakeup function of port p1 3 is not used (register k1 3 = 0 ), clear bits 2 and 3 of register i1 before system enters to the ram back-up mode. (refer to figure 3.3.2 ? ?? ? ? depending on the input state of the p1 3 /int pin, the external 0 interrupt request flag (exf0) may be set when the bit 2 of register i1 is changed. in order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register v1 to 0 (refer to figure 3.3.3 ? 0 after executing at least one instruction (refer to figure 3.3.3 ? ? la 4 ; ( ??? ? ? ?? ? ? ?
3.3 list of precautions 3-31 4502 group appendix rev.2.01 feb 02, 2005 rej09b0193-0201 3.3.5 notes on timer (1) prescaler stop the prescaler operation to change its frequency dividing ratio. (2) count source stop timer 1 or 2 counting to change its count source. (3) reading the count values stop timer 1 or 2 counting and then execute the tab1 or tab2 instruction to read its data. (4) writing to the timer stop timer 1 or 2 counting and then execute the t1ab or t2ab instruction to write its data. (5) writing to reload register r1 when writing data to reload register r1 while timer 1 is operating, avoid a timing when timer 1 underflow. (6) timer 1 and timer 2 count start timing and count time when operation starts count starts from the first rising edge of the count source (2) after timer 1 and timer 2 operations start (1). time to first underflow (3) is shorter (for up to 1 period of the count source) than time among next underflow (4) by the timing to start the timer and count source operations after count starts. when selecting cntr input as the count source of timer 2, timer 2 operates synchronizing with the falling edge of cntr input. parameter timer external input period (h and l pulse width) condition high-speed mode middle-speed mode low-speed mode default mode min. 3/f(x in ) 6/f(x in ) 12/f(x in ) 24/f(x in ) unit s typ. max. rating value fig. 3.3.4 timer count start timing and count time when operation starts (t1, t2) (1) timer count source timer value timer underflow signal 321 032 103 2 count source (cntr input) (2) (3) (4) (7) watchdog timer the watchdog timer function is valid after system is released from reset. when not using the watchdog timer function, execute the dwdt instruction and the wrst instruction continuously, and clear the wef flag to 0 to stop the watchdog timer function. the watchdog timer function is valid after system is returned from the ram back-up. when not using the watchdog timer function, execute the dwdt instruction and the wrst instruction continu- ously every system is returned from the ram back-up, and stop the watchdog timer function. (8) pulse width input to cntr pin table 3.3.2 shows the recommended operating condition of pulse width input to cntr pin. table 3.3.2 recommended operating condition of pulse width input to cntr pin
3.3 list of precautions 3-32 rev.2.01 feb 02, 2005 4502 group appendix rej09b0193-0201 3.3.6 notes on a/d conversion (1) note when the a/d conversion starts again when the a/d conversion starts again with the adst instruction during a/d conversion, the previous input data is invalidated and the a/d conversion starts again. (2) a/d converter-1 each analog input pin is equipped with a capacitor which is used to compare the analog voltage. accordingly, when the analog voltage is input from the circuit with high-impedance and, charge/ discharge noise is generated and the sufficient a/d accuracy may not be obtained. therefore, reduce the impedance or, connect a capacitor (0.01 f to 1 f) to analog input pins. figure 3.3.5 shows the analog input external circuit example-1. when the overvoltage applied to the a/d conversion circuit may occur, connect an external circuit in order to keep the voltage within the rated range as shown the figure 3.3.6. in addition, test the application products sufficiently. fig. 3.3.5 analog input external circuit example-1 (3) notes for the use of a/d conversion 2 when the operating mode of the a/d converter is changed from the comparator mode to the a/d conversion mode with bit 3 of register q1 in a program, be careful about the following notes. ?clear bit 2 of register v2 to ??to change the operating mode of the a/d converter from the comparator mode to the a/d conversion mode with bit 3 of register q1 (refer to figure 3.3.7 ? ). ?the a/d conversion completion flag (adf) may be set when the operating mode of the a/d converter is changed from the comparator mode to the a/d conversion mode. accordingly, set a value to bit 3 of register q1, and execute the snzad instruction to clear the adf flag. do not change the operating mode (both a/d conversion mode and comparator mode) of a/d converter with bit 3 of register q1 during operating the a/d converter. fig. 3.3.6 analog input external circuit example-2 fig. 3.3.7 a/d converter operating mode program example clear bit 2 of register v2 to ??...... ? change of the operating mode of the a/d converter from the comparator mode to the a/d conversion mode clear the adf flag to ??with the snzad instruction execute the nop instruction for the case when a skip is performed with the snzad instruction sensor a in ( note ) n o t e : a p p l y t h e v o l t a g e w i t h i n t h e s p e c i f i c a t i o n s t o a n a n a l o g i n p u t p i n . sensor a in a b o u t 1 k ?
3.3 list of precautions 3-33 4502 group appendix rev.2.01 feb 02, 2005 rej09b0193-0201 (4) a/d converter is used at the comparator mode the analog input voltage is higher than the comparison voltage as a result of comparison, the contents of adf flag retains 0, not set to 1. in this case, the a/d interrupt does not occur even when the usage of the a/d interrupt is enabled. accordingly, consider the time until the comparator operation is completed, and examine the state of adf flag by software. the comparator operation is completed after 8 machine cycles. (5) analog input pins even when p2 0 /a in0 , p2 1 /a in1 , p3 0 /a in2 and p3 1 /a in3 are set to pins for analog input, they continue to function as p2 and p3 i/o. accordingly, when any of them are used as these ports and others are used as analog input pins, make sure to set the outputs of pins that are set for analog input to 1. also, the port input function of the pin functions as an analog input is undefined. (6) tala instruction when the tala instruction is executed, the low-order 2 bits of register ad is transferred to the high- order 2 bits of register a, and simultaneously, the low-order 2 bits of register a is 0. (7) recommended operating conditions when using a/d converter the recommended operating conditions of supply voltage and system clock frequency when using a/ d converter are different from those when not using a/d converter. table 3.3.3 shows the recommended operating conditions when using a/d converter. table 3.3.3 recommended operating conditions (when using a/d converter) parameter system clock frequency (at ceramic resonance or rc oscillation) ( note 2 ) system clock frequency (ceramic resonance selected, at external clock input) condition v dd = vrst to 5.5 v (high-speed mode) v dd = vrst to 5.5 v (middle-speed mode) v dd = vrst to 5.5 v (low-speed mode) v dd = vrst to 5.5 v (default mode) v dd = vrst to 5.5 v (high-speed mode) v dd = vrst to 5.5 v (middle-speed mode) v dd = vrst to 5.5 v (low-speed mode) v dd = vrst to 5.5 v (default mode) limits min. 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 max. 4.4 2.2 1.1 0.5 3.2 1.6 0.8 0.4 unit mhz typ. duty 40 % to 60 % notes 1: vrst: detection voltage of voltage drop detection circuit. 2: the frequency at rc oscillation is affected by a capacitor, a resistor and a microcomputer. so, set the constants within the range of the frequency limits. 3.3.7 notes on reset (1) register initial value the initial value of the following registers are undefined after system is released from reset. after system is released from reset, set initial values. register z (2 bits) register d (3 bits) register e (8 bits) (2) power-on reset reset can be automatically performed at power on (power-on reset) by the built-in power-on reset circuit. when the built-in power-on reset circuit is used, the time for the supply voltage to rise from 0 v to 2.0 v must be set to 100 s or less. if the rising time exceeds 100 s, connect a capacitor between the reset pin and v ss at the shortest distance, and input l level to reset pin until the value of supply voltage reaches the minimum operating voltage.
3.3 list of precautions 3-34 rev.2.01 feb 02, 2005 4502 group appendix rej09b0193-0201 3.3.8 notes on ram back-up (1) key-on wakeup function after setting ports (p0, p1, d 2 /c, d 3 /k, p2 0 /a in0 and p2 1 /a in1 specified with register k0 k2) which key- on wakeup function is valid to h, execute the pof or pof2 instruction. if one of ports which key-on wakeup function is valid is in the l level state, system returns from the ram back-up after the pof or pof2 instruction is executed. (2) pof instruction, pof2 instruction execute the pof or pof2 instruction immediately after executing the epof instruction to enter the ram back-up state. note that system cannot enter the ram back-up state when executing only the pof or pof2 instruction. be sure to disable interrupts by executing the di instruction before executing the epof instruction and the pof or pof2 instruction. (3) return from ram back-up after system returns from ram back-up, set the undefined registers and flags. the initial value of the following registers are undefined at ram back-up. after system is returned from ram back-up, set initial values. register z (2 bits) register x (4 bits) register y (4 bits) register d (3 bits) register e (8 bits) (4) watchdog timer the watchdog timer function is valid after system is returned from the ram back-up. when not using the watchdog timer function, execute the dwdt instruction and the wrst instruction continuously every system is returned from the ram back-up, and stop the watchdog timer function. (5) p1 3 /int pin when the bit 3 of register i1 is cleared, the ram back-up mode is selected and the input of int pin is disabled, be careful about the following notes. when the key-on wakeup function of port p1 3 is not used (register k1 3 = 0 ), clear bits 2 and 3 of register i1 before system enters to the ram back-up mode. (6) external clock when the external signal clock is used as the source oscillation (f(x in )), note that the ram back-up mode ( pof and pof2 instructions) cannot be used.
3.3 list of precautions 3-35 4502 group appendix rev.2.01 feb 02, 2005 rej09b0193-0201 3.3.9 notes on oscillation control (1) clock control execute the cmck or the crck instruction in the initial setting routine of program (executing it in addres 0 in page 0 is recommended). the oscillation circuit by the cmck or crck instruction can be selected only at once. the oscillation circuit corresponding to the first executed one of these two instructions is valid. other oscillation circuits and the on-chip oscillator stop. (2) on-chip oscillator the clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. be careful that variable frequencies when designing application products. also, the oscillation stabilize wait time after system is released from reset is generated by the on- chip oscillator clock. when considering the oscillation stabilize wait time after system is released from reset, be careful that the variable frequency of the on-chip oscillator clock. (3) external clock when the external signal clock is used as the source oscillation (f(x in )), note that the ram back-up mode ( pof and pof2 instructions) cannot be used. (4) value of a part connected to an oscillator values of a capacitor and a resistor of the oscillation circuit depend on the connected oscillator and the board. accordingly, consult the oscillator manufacturer for values of each part connected the oscillator. 3.3.10 electric characteristic differences between mask rom and one time prom version mcu there are differences in electric characteristics, operation margin, noise immunity, and noise radiation between mask rom and one time prom version mcus due to the difference in the manufacturing processes. when manufacturing an application system with the one time prom version and then switching to use of the mask rom version, please perform sufficient evaluations for the commercial samples of the mask rom version. 3.3.11 note on power source voltage when the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. in a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation.
3.4 notes on noise 3-36 rev.2.01 feb 02, 2005 4502 group appendix rej09b0193-0201 3.4 notes on noise countermeasures against noise are described below. the following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use. 3.4.1 shortest wiring length the wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer. the shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer. (1) package select the smallest possible package to make the total wiring length short. the wiring length depends on a microcom- puter package. use of a small package, for example qfp and not dip, makes the total wiring length short to reduce influence of noise. fig. 3.4.1 selection of packages (2) wiring for reset input pin make the length of wiring which is connected to the reset input pin as short as possible. especially, connect a capacitor across the reset input pin and the v ss pin with the shortest possible wiring. in order to reset a microcomputer correctly, 1 machine cycle or more of the width of a pulse input into the reset pin is required. if noise having a shorter pulse width than this is input to the reset input pin, the reset is released before the internal state of the microcomputer is completely initialized. this may cause a program runaway. dip sdip sop qfp fig. 3.4.2 wiring for the reset input pin reset reset circuit noise v ss v ss reset circuit v ss reset v ss n.g. o.k.
3.4 notes on noise 3-37 4502 group appendix rev.2.01 feb 02, 2005 rej09b0193-0201 (3) wiring for clock input/output pins make the length of wiring which is connected to clock i/o pins as short as possible. make the length of wiring across the grounding lead of a capacitor which is connected to an oscillator and the v ss pin of a microcomputer as short as possible. separate the v ss pattern only for oscillation from other v ss patterns. fig. 3.4.3 wiring for clock i/o pins if noise enters clock i/o pins, clock waveforms may be deformed. this may cause a program failure or program runaway. also, if a potential difference is caused by the noise between the v ss level of a microcomputer and the v ss level of an oscillator, the correct clock will not be input in the microcomputer. fig. 3.4.4 wiring for cnv ss pin noise x in x out v ss x in x out v ss n.g. o.k. noise cnv ss v ss cnv ss v ss n.g. o.k. (4) wiring to cnv ss pin connect the cnv ss pin to the v ss pin with the shortest possible wiring. the operation mode of a microcomputer is influenced by a potential at the cnv ss pin. if a potential difference is caused by the noise between pins cnv ss and v ss , the operation mode may become unstable. this may cause a microcomputer malfunction or a program runaway.
3.4 notes on noise 3-38 rev.2.01 feb 02, 2005 4502 group appendix rej09b0193-0201 (5) wiring to v pp pin of built-in prom version in the built-in prom version of the 4502 group, the cnv ss pin is also used as the built-in prom power supply input pin v pp . connect an approximately 5 k ? resistor to the v pp pin the shortest possible in series and also to the v ss pin. when not connecting the resistor, make the length of wiring between the v pp pin and the v ss pin the shortest possible (refer to figure 3.4.5 ) note: even when a circuit which included an approximately 5 k ? resistor is used in the mask rom version, the microcomputer operates correctly. the v pp pin of the built-in prom version is the power source input pin for the built- in prom. when programming in the built- in prom, the impedance of the v pp pin is low to allow the electric current for writing flow into the prom. because of this, noise can enter easily. if noise enters the v pp pin, abnormal instruction codes or data are read from the built-in prom, which may cause a program runaway. fig. 3.4.5 wiring for the v pp pin of the built-in prom version cnv ss /v pp when the v pp pin is also used as the cnv ss pin v ss in the shortest distance approximately 5k ? connect an approximately 0.1 f bypass capacitor across the v ss line and the v dd line as follows: connect a bypass capacitor across the v ss pin and the v dd pin at equal length. connect a bypass capacitor across the v ss pin and the v dd pin with the shortest possible wiring. use lines with a larger diameter than other signal lines for v ss line and v dd line. connect the power source wiring via a bypass capacitor to the v ss pin and the v dd pin. fig. 3.4.6 bypass capacitor across the v ss line and the v dd line v ss v dd aa aa aa aa aa aa v ss v dd aa aa aa aa aa aa aa aa aa n.g. o.k.
3.4 notes on noise 3-39 4502 group appendix rev.2.01 feb 02, 2005 rej09b0193-0201 3.4.3 wiring to analog input pins connect an approximately 100 ? to 1 k ? resistor to an analog signal line which is connected to an analog input pin in series. besides, connect the resistor to the microcomputer as close as possible. connect an approximately 1000 pf capacitor across the v ss pin and the analog input pin. besides, connect the capacitor to the v ss pin as close as possible. also, connect the capacitor across the analog input pin and the v ss pin at equal length. signals which is input in an analog input pin (such as an a/d converter/comparator input pin) are usually output signals from sensor. the sensor which detects a change of event is installed far from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily. this long wiring functions as an antenna which feeds noise into the microcomputer, which causes noise to an analog input pin. fig. 3.4.7 analog signal line and a resistor and a capacitor analog input pin v ss noise thermistor microcomputer n.g. o.k. (note) note : the resistor is used for dividing resistance with a thermistor. 3.4.4 oscillator concerns take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) keeping oscillator away from large current signal lines install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. in the system using a microcomputer, there are signal lines for controlling motors, leds, and thermal heads or others. when a large current flows through those signal lines, strong noise occurs because of mutual inductance. fig. 3.4.8 wiring for a large current signal line x in x out v ss m microcomputer mutual inductance large current gnd
3.4 notes on noise 3-40 rev.2.01 feb 02, 2005 4502 group appendix rej09b0193-0201 fig. 3.4.9 wiring to a signal line where potential levels change frequently (3) oscillator protection using v ss pattern as for a two-sided printed circuit board, print a v ss pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. connect the v ss pattern to the microcomputer v ss pin with the shortest possible wiring. besides, separate this v ss pattern from other v ss patterns. x in x out v ss cntr do not cross n.g. aaa aaa aaa aaa a a a aaa a a a a a aa aa x in x out v ss an example of v ss patterns on the underside of a printed circuit board oscillator wiring pattern example separate the v ss line for oscillation from other v ss lines 3.4.5 setup for i/o ports setup i/o ports using hardware and software as follows: connect a resistor of 100 ? or more to an i/o port in series. as for an input port, read data several times by a program for checking whether input levels are equal or not. as for an output port or an i/o port, since the output data may reverse because of noise, rewrite data to its output latch at fixed periods. rewrite data to pull-up control registers at fixed periods. 3.4.6 providing of watchdog timer function by software if a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. this is equal to or more effective than program runaway detection by a hardware watchdog timer. the following shows an example of a watchdog timer provided by software. in the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. this example assumes that interrupt processing is repeated multiple times in a single main routine processing. (2) installing oscillator away from signal lines where potential levels change frequently install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. signal lines where potential levels change frequently (such as the cntr pin signal line) may affect other lines at signal rising edge or falling edge. if such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. fig. 3.4.10 v ss pattern on the underside of an oscillator
3.4 notes on noise 3-41 4502 group appendix rev.2.01 feb 02, 2005 rej09b0193-0201 assigns a single word of ram to a software watchdog timer (swdt) and writes the initial value n in the swdt once at each execution of the main routine. the initial value n should satisfy the following condition: n+1 as the main routine execution cycle may change because of an interrupt processing or others, the initial value n should have a margin. watches the operation of the interrupt processing routine by comparing the swdt contents with counts of interrupt processing after the initial value n has been set. detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: if the swdt contents do not change after interrupt processing. decrements the swdt contents by 1 at each interrupt processing. determines that the main routine operates normally when the swdt contents are reset to the initial value n at almost fixed cycles (at the fixed interrupt processing count). detects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: if the swdt contents are not initialized to the initial value n but continued to decrement and if they reach 0 or less. fig. 3.4.11 watchdog timer by software (counts of interrupt processing executed in each main routine) main routine (swdt) n ei main processing (swdt) interrupt processing routine errors n interrupt processing routine (swdt) (swdt) 1 interrupt processing (swdt) main routine errors > 0 0 rti return =n? 0? n
3-42 rev.2.01 feb 02, 2005 4502 group appendix rej09b0193-0201 3.5 package outline 3.5 package outline f 1 12 13 24 * 2 * 1 * 3 index mark y e h e e b p d a c detail f a 1 a 2 l include trim offset. dimension " * 3" does not note) do not include mold flash. dimensions " * 1" and " * 2" 1. 2. a 1 0 0.1 0.2 previous code jeita package code renesas code prsp0024ga-a 24p2q-a mass[typ.] 0.2g p-ssop24-5.3x10.1-0.80 0.25 0.2 0.18 0.45 0.35 0.3 max nom min dimension in millimeters symbol reference 10.2 10.1 10.0 d 5.4 5.3 5.2 e 1.8 a 2 8.1 7.8 7.5 2.1 a 0.8 0.6 0.4 l 8 0 c 0.8 e 0.10 y h e b p 0.65 0. 95
renesas 4-bit cisc single-chip microcomputer user? manual 4502 group publication data : rev.1.00 oct 09, 2002 rev.2.01 feb 02, 2005 published by : sales strategic planning div. renesas technology corp. 2005. renesas technology corp., all rights reserved. printed in japan.
4502 group user's manual 2-6-2, ote-machi, chiyoda-ku, tokyo, 100-0004, japan

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